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/freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
283 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
[all …]
DPPCCallingConv.td36 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
68 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
100 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
114 CCIfType<[v16i8, v8i16, v4i32, v4f32],
DPPCISelLowering.cpp373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom); in PPCTargetLowering()
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
757 assert(N->getValueType(0) == MVT::v16i8 && in isVMerge()
795 assert(N->getValueType(0) == MVT::v16i8 && in isVSLDOIShuffleMask()
831 assert(N->getValueType(0) == MVT::v16i8 && in isSplatShuffleMask()
2032 case MVT::v16i8: in LowerFormalArguments_32SVR4()
2278 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { in LowerFormalArguments_64SVR4()
[all …]
DPPCISelDAGToDAG.cpp638 if (VecVT == MVT::v16i8) in getVCmpInst()
652 if (VecVT == MVT::v16i8) in getVCmpInst()
665 if (VecVT == MVT::v16i8) in getVCmpInst()
697 case MVT::v16i8: in getVCmpEQInst()
1325 VT = MVT::v16i8; in Select()
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp227 { ISD::SHL, MVT::v16i8, 1 }, // psllw. in getArithmeticInstrCost()
232 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. in getArithmeticInstrCost()
237 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
259 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence. in getArithmeticInstrCost()
264 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized. in getArithmeticInstrCost()
269 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized. in getArithmeticInstrCost()
280 { ISD::SDIV, MVT::v16i8, 16*20 }, in getArithmeticInstrCost()
284 { ISD::UDIV, MVT::v16i8, 16*20 }, in getArithmeticInstrCost()
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, in getCastInstrCost()
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, in getCastInstrCost()
[all …]
DX86InstrSSE.td297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
313 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
347 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
[all …]
DX86CallingConv.td43 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
240 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
268 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
291 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
317 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
339 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
408 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
417 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
DX86InstrFragmentsSIMD.td78 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
236 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
239 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
240 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
451 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
DX86InstrAVX512.td20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
[all …]
DX86ISelLowering.cpp935 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); in resetOperationActions()
940 setOperationAction(ISD::ADD, MVT::v16i8, Legal); in resetOperationActions()
946 setOperationAction(ISD::SUB, MVT::v16i8, Legal); in resetOperationActions()
960 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in resetOperationActions()
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); in resetOperationActions()
971 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { in resetOperationActions()
997 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { in resetOperationActions()
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in resetOperationActions()
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in resetOperationActions()
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); in resetOperationActions()
[all …]
DX86RegisterInfo.td436 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
461 def VR128X : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DSITypeRewriter.cpp38 Type *v16i8; member in __anon3a32eecf0111::SITypeRewriter
59 v16i8 = VectorType::get(Type::getInt8Ty(M.getContext()), 16); in doInitialization()
87 if (ElemTy == v16i8) { in visitLoadInst()
110 if (Arg->getType() == v16i8) { in visitCallInst()
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMCallingConv.td28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
89 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
139 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
149 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
167 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
179 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMTargetTransformInfo.cpp230 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
231 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
234 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
460 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 } in getShuffleCost()
514 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
515 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
516 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
517 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
DARMInstrNEON.td1032 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1327 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1982 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
2024 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
3153 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3156 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3189 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3190 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3266 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3268 v16i8, v16i8, OpNode, Commutable>;
[all …]
DARMRegisterInfo.td302 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
310 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
314 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
327 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
DARMISelDAGToDAG.cpp1805 case MVT::v16i8: OpcodeIndex = 0; break; in SelectVLD()
1941 case MVT::v16i8: OpcodeIndex = 0; break; in SelectVST()
2270 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); in SelectVTBL()
2761 case MVT::v16i8: Opc = ARM::VZIPq8; break; in Select()
2781 case MVT::v16i8: Opc = ARM::VUZPq8; break; in Select()
2800 case MVT::v16i8: Opc = ARM::VTRNq8; break; in Select()
3311 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); in Select()
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrNEON.td94 [(set (v16i8 VPR128:$Rd),
95 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
149 [(set (v16i8 VPR128:$Rd),
150 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
255 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
268 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
358 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
412 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
445 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
477 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
[all …]
DAArch64RegisterInfo.td167 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
175 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
/freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.h74 v16i8 = 23, // 16 x i8 enumerator
216 return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 || in is128BitVector()
277 case v16i8: in getVectorElementType()
321 case v16i8: in getVectorNumElements()
408 case v16i8: in getSizeInBits()
517 if (NumElements == 16) return MVT::v16i8; in getVectorVT()
DValueTypes.td46 def v16i8 : ValueType<128, 23>; // 16 x i8 vector value
/freebsd-9-stable/contrib/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td149 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
196 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
200 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
204 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
208 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
212 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
218 (v16i8 (build_vector node:$e0, node:$e0,
264 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
268 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
272 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
[all …]
DMipsSEInstrInfo.cpp205 else if (RC->hasType(MVT::v16i8)) in storeRegToStack()
246 else if (RC->hasType(MVT::v16i8)) in loadRegFromStack()
/freebsd-9-stable/contrib/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp68 DecodePALIGNRMask(MVT::v16i8, in EmitAnyX86InstComments()
152 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask); in EmitAnyX86InstComments()
225 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask); in EmitAnyX86InstComments()
/freebsd-9-stable/contrib/llvm/lib/IR/
DValueTypes.cpp141 case MVT::v16i8: return "v16i8"; in getEVTString()
209 case MVT::v16i8: return VectorType::get(Type::getInt8Ty(Context), 16); in getTypeForEVT()

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