| /freebsd-9-stable/contrib/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 869 "subc.b\t{$src2, $dst}",
874 "subc.w\t{$src2, $dst}",
880 "subc.b\t{$src2, $dst}",
885 "subc.w\t{$src2, $dst}",
891 "subc.b\t{$src2, $dst}",
896 "subc.w\t{$src2, $dst}",
903 "subc.b\t{$src, $dst}",
908 "subc.w\t{$src, $dst}",
914 "subc.b\t{$src, $dst}",
919 "subc.w\t{$src, $dst}",
[all …]
|
| /freebsd-9-stable/contrib/gcc/ |
| D | print-rtl.c | 499 enum rtx_code subc = GET_CODE (sub); in print_rtx() local
503 if (subc == NOTE in print_rtx()
514 if (subc != CODE_LABEL) in print_rtx()
|
| D | FSFChangeLog.11 | 3161 (addc, subc, ashlsi_c): New insns.
|
| D | ChangeLog-2003 | 1673 (subc): Fix description of new T value.
|
| D | ChangeLog-2002 | 23821 (add,addc1,addsi3,subc,subc1,*subsi3_internal,
|
| /freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 775 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
777 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
780 // subc because we prefer addc for constants.
785 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
786 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
787 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
789 defm : ZXB<subc, GR64, SLGFR>;
|
| /freebsd-9-stable/contrib/llvm/patches/ |
| D | patch-r262261-llvm-r198157-sparc.diff | 217 - defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
218 + defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 324 def SubCCV4I32 : VecBinaryOp<V4AsmStr<"sub.cc.s32">, subc, V4I32Regs,
326 def SubCCV2I32 : VecBinaryOp<V2AsmStr<"sub.cc.s32">, subc, V2I32Regs,
332 def SubCCCV4I32 : VecBinaryOp<V4AsmStr<"subc.cc.s32">, sube, V4I32Regs,
334 def SubCCCV2I32 : VecBinaryOp<V2AsmStr<"subc.cc.s32">, sube, V2I32Regs,
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| D | NVPTXInstrInfo.td | 400 defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
403 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
|
| /freebsd-9-stable/contrib/binutils/gas/doc/ |
| D | c-sh.texi | 309 sett subc Rm,Rn
|
| /freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 436 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
439 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
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| D | PPCInstrInfo.td | 1590 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2024 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2430 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2431 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 481 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
|
| /freebsd-9-stable/contrib/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 345 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
|
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 439 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
441 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
443 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
840 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 1306 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
|
| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 1218 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
|
| D | Mips16InstrInfo.td | 1404 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
|
| /freebsd-9-stable/contrib/binutils/opcodes/ |
| D | ChangeLog-0001 | 724 * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc.
|
| /freebsd-9-stable/contrib/gdb/ |
| D | md5.sum | 4183 f32638a3919a1385e630a7e29518e0ed sim/testsuite/sim/fr30/subc.cgs
|