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Searched refs:ror (Results 1 – 25 of 34) sorted by relevance

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/freebsd-9-stable/contrib/compiler-rt/lib/arm/
Dbswapdi2.S22 eor r2, r0, r0, ror #16
25 eor r2, r2, r0, ror #8
27 eor r0, r1, r1, ror #16
30 eor r0, r0, r1, ror #8
Dbswapsi2.S21 eor r1, r0, r0, ror #16
24 eor r0, r1, r0, ror #8
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrShiftRotate.td585 "ror{b}\t{%cl, $dst|$dst, cl}",
588 "ror{w}\t{%cl, $dst|$dst, cl}",
591 "ror{l}\t{%cl, $dst|$dst, cl}",
594 "ror{q}\t{%cl, $dst|$dst, cl}",
599 "ror{b}\t{$src2, $dst|$dst, $src2}",
602 "ror{w}\t{$src2, $dst|$dst, $src2}",
607 "ror{l}\t{$src2, $dst|$dst, $src2}",
612 "ror{q}\t{$src2, $dst|$dst, $src2}",
618 "ror{b}\t$dst",
622 "ror{w}\t$dst",
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h32 ror, enumerator
51 case ARM_AM::ror: return "ror"; in getShiftOpcStr()
62 case ARM_AM::ror: return 3; in getShiftOpcEncoding()
DARMMCCodeEmitter.cpp187 case ARM_AM::ror: in getShiftOp()
1204 case ARM_AM::ror: SBits = 0x7; break; in getSORegRegOpValue()
1248 case ARM_AM::ror: SBits = 0x6; break; in getSORegImmOpValue()
1364 case ARM_AM::ror: SBits = 0x6; break; in getT2SORegOpValue()
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h29 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
DARMCodeEmitter.cpp420 case ARM_AM::ror: in getShiftOp()
953 case ARM_AM::ror: SBits = 0x7; break; in getMachineSoRegOpValue()
967 case ARM_AM::ror: SBits = 0x6; break; in getMachineSoRegOpValue()
DARMInstrThumb.td1122 "ror", "\t$Rdn, $Rm",
DARMInstrInfo.td5518 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5534 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
/freebsd-9-stable/contrib/gcc/config/arm/
Dlib1funcs.asm593 ror curbit, work
603 ror curbit, work
613 ror curbit, work
679 ror curbit, work
687 ror curbit, work
695 ror curbit, work
/freebsd-9-stable/sys/contrib/octeon-sdk/
Dcvmx-sli-defs.h3140 uint64_t ror : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes. member
3150 uint64_t ror : 32;
3375 uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and member
3381 uint64_t ror : 1;
3760 uint64_t ror : 32; /**< ADDRTYPE<0> for the packet output ring reads that member
3769 uint64_t ror : 32;
Dcvmx-npi-defs.h1865 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of member
1868 uint64_t ror : 1;
1901 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of member
1904 uint64_t ror : 1;
3247 uint64_t ror : 1; /**< Relax Read on read. */ member
3253 uint64_t ror : 1;
3272 uint64_t ror : 1; /**< Relax Read on read. */ member
3278 uint64_t ror : 1;
Dcvmx-npei-defs.h5535 uint64_t ror : 1; /**< Relaxed Ordering for Reads. */ member
5541 uint64_t ror : 1;
6612 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding member
6615 uint64_t ror : 32;
6803 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of member
6806 uint64_t ror : 1;
7197 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding member
7200 uint64_t ror : 32;
Dcvmx-pcie.c654 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */ in __cvmx_pcie_rc_initialize_gen1()
1500 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */ in cvmx_pcie_ep_initialize()
/freebsd-9-stable/sys/arm/arm/
Din_cksum_arm.S79 movne r2, r2, ror #8
Dsupport.S2662 mov r2, r2, ror #8 /* r2 = 1..0 */
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1154 Shift = ARM_AM::ror; in DecodeSORegImmOperand()
1158 if (Shift == ARM_AM::ror && imm == 0) in DecodeSORegImmOperand()
1193 Shift = ARM_AM::ror; in DecodeSORegRegOperand()
1547 Opc = ARM_AM::ror; in DecodeAddrMode2IdxInstruction()
1553 if (Opc == ARM_AM::ror && amt == 0) in DecodeAddrMode2IdxInstruction()
1592 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1596 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
/freebsd-9-stable/contrib/binutils/gas/doc/
Dc-avr.texi348 1001010rrrrr0111 ror r
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp2711 .Case("ror", ARM_AM::ror) in tryParseShiftRegister()
2758 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || in tryParseShiftRegister()
4421 St = ARM_AM::ror; in parseMemRegOffsetShift()
4450 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || in parseMemRegOffsetShift()
7005 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
7039 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
7071 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
7096 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
/freebsd-9-stable/contrib/binutils/opcodes/
DChangeLog-0203849 Note that hardware rotate instructions (ror, rorv) can be
904 * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
905 "dror" entries, and reorder the remaining "dror" and "ror" entries.
Di386-opc.tbl250 ror, 2, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp1…
251 ror, 2, 0xc0, 0x1, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|…
252 ror, 2, 0xd2, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8…
253 ror, 1, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp…
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
/freebsd-9-stable/contrib/gcc/config/i386/
Di386.md12867 "ror{q}\t%0"
12881 ror{q}\t{%2, %0|%0, %2}
12882 ror{q}\t{%b2, %0|%0, %b2}"
12901 "ror{l}\t%0"
12916 "ror{l}\t%k0"
12930 ror{l}\t{%2, %0|%0, %2}
12931 ror{l}\t{%b2, %0|%0, %b2}"
12943 ror{l}\t{%2, %k0|%k0, %2}
12944 ror{l}\t{%b2, %k0|%k0, %b2}"
12963 "ror{w}\t%0"
[all …]
/freebsd-9-stable/lib/libc/arm/string/
Dmemcpy_xscale.S1510 mov r2, r2, ror #8 /* r2 = 1..0 */
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1793 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1812 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1950 def : InstAlias<"ror $Rd, $Rs, $LSB",
1952 def : InstAlias<"ror $Rd, $Rs, $LSB",

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