| /freebsd-9-stable/sys/mips/atheros/ |
| D | ar71xx_chip.c | 92 uint32_t pll; in ar71xx_chip_detect_sys_frequency() local
96 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_chip_detect_sys_frequency()
98 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; in ar71xx_chip_detect_sys_frequency()
101 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_chip_detect_sys_frequency()
104 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_chip_detect_sys_frequency()
107 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_chip_detect_sys_frequency()
145 uint32_t pll; in ar71xx_chip_set_pll_ge0() local
149 pll = PLL_ETH_INT_CLK_10; in ar71xx_chip_set_pll_ge0()
152 pll = PLL_ETH_INT_CLK_100; in ar71xx_chip_set_pll_ge0()
155 pll = PLL_ETH_INT_CLK_1000; in ar71xx_chip_set_pll_ge0()
[all …]
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| D | ar91xx_chip.c | 70 uint32_t pll; in ar91xx_chip_detect_sys_frequency() local
74 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); in ar91xx_chip_detect_sys_frequency()
76 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); in ar91xx_chip_detect_sys_frequency()
81 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; in ar91xx_chip_detect_sys_frequency()
84 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; in ar91xx_chip_detect_sys_frequency()
118 uint32_t pll; in ar91xx_chip_set_pll_ge0() local
122 pll = AR91XX_PLL_VAL_10; in ar91xx_chip_set_pll_ge0()
125 pll = AR91XX_PLL_VAL_100; in ar91xx_chip_set_pll_ge0()
128 pll = AR91XX_PLL_VAL_1000; in ar91xx_chip_set_pll_ge0()
136 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT); in ar91xx_chip_set_pll_ge0()
[all …]
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| D | ar724x_chip.c | 71 uint32_t pll; in ar724x_chip_detect_sys_frequency() local
75 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); in ar724x_chip_detect_sys_frequency()
77 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); in ar724x_chip_detect_sys_frequency()
80 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); in ar724x_chip_detect_sys_frequency()
85 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; in ar724x_chip_detect_sys_frequency()
88 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; in ar724x_chip_detect_sys_frequency()
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| D | ar71xxreg.h | 506 ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift) in ar71xx_write_pll() argument
518 ATH_WRITE_REG(pll_reg, pll); in ar71xx_write_pll()
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| /freebsd-9-stable/sys/dev/drm2/radeon/ |
| D | radeon_display.c | 748 static void avivo_get_fb_div(struct radeon_pll *pll, in avivo_get_fb_div() argument
758 *fb_div = tmp / pll->reference_freq; in avivo_get_fb_div()
759 *frac_fb_div = tmp % pll->reference_freq; in avivo_get_fb_div()
761 if (*fb_div > pll->max_feedback_div) in avivo_get_fb_div()
762 *fb_div = pll->max_feedback_div; in avivo_get_fb_div()
763 else if (*fb_div < pll->min_feedback_div) in avivo_get_fb_div()
764 *fb_div = pll->min_feedback_div; in avivo_get_fb_div()
767 static u32 avivo_get_post_div(struct radeon_pll *pll, in avivo_get_post_div() argument
772 if (pll->flags & RADEON_PLL_USE_POST_DIV) in avivo_get_post_div()
773 return pll->post_div; in avivo_get_post_div()
[all …]
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| D | atombios_crtc.c | 1002 struct radeon_pll *pll; in atombios_crtc_set_pll() local
1007 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1010 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1015 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1020 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1021 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1022 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1026 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1029 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1032 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
[all …]
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| D | radeon_legacy_crtc.c | 727 struct radeon_pll *pll; in radeon_set_pll() local
750 pll = &rdev->clock.p2pll; in radeon_set_pll()
752 pll = &rdev->clock.p1pll; in radeon_set_pll()
754 pll->flags = RADEON_PLL_LEGACY; in radeon_set_pll()
757 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in radeon_set_pll()
759 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in radeon_set_pll()
771 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; in radeon_set_pll()
786 pll->flags |= RADEON_PLL_USE_REF_DIV; in radeon_set_pll()
794 radeon_compute_pll_legacy(pll, mode->clock, in radeon_set_pll()
825 pll_gain = radeon_compute_pll_gain(pll->reference_freq, in radeon_set_pll()
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| D | radeon_legacy_tv.c | 245 struct radeon_pll *pll; in radeon_legacy_tv_get_std_mode() local
249 pll = &rdev->clock.p2pll; in radeon_legacy_tv_get_std_mode()
251 pll = &rdev->clock.p1pll; in radeon_legacy_tv_get_std_mode()
254 *pll_ref_freq = pll->reference_freq; in radeon_legacy_tv_get_std_mode()
259 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode()
264 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode()
437 struct radeon_pll *pll; in radeon_legacy_tv_init_restarts() local
441 pll = &rdev->clock.p2pll; in radeon_legacy_tv_init_restarts()
443 pll = &rdev->clock.p1pll; in radeon_legacy_tv_init_restarts()
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| D | radeon_mode.h | 573 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
581 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
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| /freebsd-9-stable/sys/dev/ath/ath_hal/ar9001/ |
| D | ar9130_phy.c | 34 uint32_t pll; in ar9130InitPLL() local
37 pll = 0x1450; in ar9130InitPLL()
39 pll = 0x1458; in ar9130InitPLL()
41 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar9130InitPLL()
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| D | ar9160_attach.c | 92 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9160InitPLL() local
95 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9160InitPLL()
97 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9160InitPLL()
100 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL()
102 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL()
104 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL()
106 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar9160InitPLL()
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| /freebsd-9-stable/sys/dev/siba/ |
| D | siba_core.c | 1110 uint32_t bufsth = 0, pll, pmu; in siba_cc_pmu1_pll0_init() local
1154 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); in siba_cc_pmu1_pll0_init()
1155 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV); in siba_cc_pmu1_pll0_init()
1156 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV; in siba_cc_pmu1_pll0_init()
1157 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV; in siba_cc_pmu1_pll0_init()
1158 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); in siba_cc_pmu1_pll0_init()
1160 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2); in siba_cc_pmu1_pll0_init()
1161 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE); in siba_cc_pmu1_pll0_init()
1162 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT; in siba_cc_pmu1_pll0_init()
1163 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; in siba_cc_pmu1_pll0_init()
[all …]
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| /freebsd-9-stable/sys/dev/ath/ath_hal/ar9002/ |
| D | ar9280_attach.c | 105 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL() local
114 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; in ar9280InitPLL()
116 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL()
119 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL()
121 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL()
123 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL()
125 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL()
127 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL()
130 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar9280InitPLL()
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| /freebsd-9-stable/sys/arm/at91/ |
| D | at91_pmcvar.h | 41 unsigned pll:1; member
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| D | at91_pmc.c | 96 .pll = 1,
106 .pll = 1,
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| /freebsd-9-stable/sys/dev/hifn/ |
| D | hifn7751.c | 303 hifn_getpllconfig(device_t dev, u_int *pll) in hifn_getpllconfig() argument
345 *pll = pllconfig; in hifn_getpllconfig()
1178 u_int32_t pll; in hifn_init_pci_registers() local
1185 pll = READ_REG_1(sc, HIFN_1_PLL); in hifn_init_pci_registers()
1186 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) in hifn_init_pci_registers()
1188 WRITE_REG_1(sc, HIFN_1_PLL, pll); in hifn_init_pci_registers()
1192 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; in hifn_init_pci_registers()
1193 WRITE_REG_1(sc, HIFN_1_PLL, pll); in hifn_init_pci_registers()
1197 pll &= ~HIFN_PLL_BP; in hifn_init_pci_registers()
1198 WRITE_REG_1(sc, HIFN_1_PLL, pll); in hifn_init_pci_registers()
[all …]
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| /freebsd-9-stable/sys/x86/cpufreq/ |
| D | powernow.c | 224 u_int pll; member
404 sc->pll * (uint64_t) sc->fsb, in pn8_setfidvid()
417 sc->pll * (uint64_t) sc->fsb, in pn8_setfidvid()
847 sc->pll = ACPI_PN8_CTRL_TO_PLL(ctrl), in pn_decode_acpi()
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| /freebsd-9-stable/sys/dev/ath/ath_hal/ar5416/ |
| D | ar5416_reset.c | 1425 uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; in ar5416InitPLL() local
1428 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5416InitPLL()
1430 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5416InitPLL()
1433 pll |= SM(0xa, AR_RTC_PLL_DIV); in ar5416InitPLL()
1435 pll |= SM(0xb, AR_RTC_PLL_DIV); in ar5416InitPLL()
1437 pll |= SM(0xb, AR_RTC_PLL_DIV); in ar5416InitPLL()
1439 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar5416InitPLL()
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| /freebsd-9-stable/sys/cam/scsi/ |
| D | scsi_ch.h | 316 u_int8_t pll[2]; /* parameter list length */ member
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| D | scsi_ch.c | 1936 scsi_ulto2b(sizeof(*parameters), scsi_cmd->pll); in scsi_send_volume_tag()
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| /freebsd-9-stable/contrib/gcc/config/mips/ |
| D | mips-ps-3d.md | 95 ; pll.ps - Pair Lower Lower
105 "pll.ps\t%0,%1,%2"
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| /freebsd-9-stable/contrib/ntp/ntpdc/ |
| D | ntpdc-opts.def | 442 .Cm pll ,
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| /freebsd-9-stable/contrib/binutils/opcodes/ |
| D | ChangeLog-9899 | 23 pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
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| /freebsd-9-stable/contrib/ntp/ |
| D | ChangeLog | 4174 * [Bug 881] Corrected display of pll offset on 64bit systems.
4529 * Solaris 2.6 has nasty kernel bugs. DO NOT enable pll!
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| /freebsd-9-stable/contrib/gcc/doc/ |
| D | extend.texi | 7692 Pair lower lower (@code{pll.ps}).
|