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Searched refs:lane (Results 1 – 25 of 29) sorted by relevance

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/freebsd-9-stable/sys/dev/drm2/
Ddrm_dp_helper.c44 int lane) in dp_get_lane_status() argument
46 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
47 int s = (lane & 1) * 4; in dp_get_lane_status()
57 int lane; in drm_dp_channel_eq_ok() local
63 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
64 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
78 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
86 int lane) in drm_dp_get_adjust_request_voltage() argument
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Ddrm_dp_helper.h333 int lane);
335 int lane);
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMInstrNEON.td216 // Register list of one D register, with byte lane subscripting.
226 // ...with half-word lane subscripting.
236 // ...with word lane subscripting.
247 // Register list of two D registers with byte lane subscripting.
257 // ...with half-word lane subscripting.
267 // ...with word lane subscripting.
277 // Register list of two Q registers with half-word lane subscripting.
287 // ...with word lane subscripting.
299 // Register list of three D registers with byte lane subscripting.
309 // ...with half-word lane subscripting.
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DARMInstrFormats.td1935 bits<3> lane;
2172 bit lane;
2179 let Inst{5} = lane;
2193 bits<2> lane;
2200 let Inst{5} = lane{1};
2201 let Inst{3} = lane{0};
2255 bits<4> lane;
DARMScheduleSwift.td1948 // Single all/lane loads.
2030 // Single/all lane store.
/freebsd-9-stable/sys/dev/drm2/i915/
Dintel_dp.c1370 int lane) in intel_get_adjust_request_voltage() argument
1372 int s = ((lane & 1) ? in intel_get_adjust_request_voltage()
1375 uint8_t l = adjust_request[lane>>1]; in intel_get_adjust_request_voltage()
1382 int lane) in intel_get_adjust_request_pre_emphasis() argument
1384 int s = ((lane & 1) ? in intel_get_adjust_request_pre_emphasis()
1387 uint8_t l = adjust_request[lane>>1]; in intel_get_adjust_request_pre_emphasis()
1458 int lane; in intel_get_adjust_train() local
1463 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
1464 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); in intel_get_adjust_train()
1465 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); in intel_get_adjust_train()
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Dintel_display.c5723 int target_clock, pixel_multiplier, lane, link_bw, factor; in ironlake_crtc_mode_set() local
5811 lane = 0; in ironlake_crtc_mode_set()
5818 &lane, &link_bw); in ironlake_crtc_mode_set()
5865 if (!lane) { in ironlake_crtc_mode_set()
5872 lane = bps / (link_bw * 8) + 1; in ironlake_crtc_mode_set()
5875 intel_crtc->fdi_lanes = lane; in ironlake_crtc_mode_set()
5879 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, in ironlake_crtc_mode_set()
/freebsd-9-stable/contrib/ofed/management/opensm/opensm/
Dosm_ucast_lash.c95 unsigned lane; member
205 int dest_switch, int lane) in remove_semipermanent_depend_for_sp() argument
218 v = cdg_vertex_matrix[lane][sw][i_next_switch]; in remove_semipermanent_depend_for_sp()
223 cdg_vertex_matrix[lane][sw][i_next_switch] = NULL; in remove_semipermanent_depend_for_sp()
237 cdg_vertex_matrix[lane][i_next_switch] in remove_semipermanent_depend_for_sp()
357 int lane) in generate_cdg_for_sp() argument
370 if (cdg_vertex_matrix[lane][sw][next_switch] == NULL) { in generate_cdg_for_sp()
389 cdg_vertex_matrix[lane][sw][next_switch] = v; in generate_cdg_for_sp()
391 v = cdg_vertex_matrix[lane][sw][next_switch]; in generate_cdg_for_sp()
430 int dest_switch, int lane) in set_temp_depend_to_permanent_for_sp() argument
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/freebsd-9-stable/sys/dev/drm2/radeon/
Datombios_dp.c304 int lane; in dp_get_adjust_train() local
306 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()
307 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in dp_get_adjust_train()
308 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in dp_get_adjust_train()
311 lane, in dp_get_adjust_train()
331 for (lane = 0; lane < 4; lane++) in dp_get_adjust_train()
332 train_set[lane] = v | p; in dp_get_adjust_train()
/freebsd-9-stable/sys/contrib/octeon-sdk/
Dcvmx-helper-errata.c306 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
309 for (lane=0; lane<4; lane++) in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
Dcvmx-sriomaintx-defs.h2969 uint32_t lane : 4; /**< Lane Number within the port. */ member
3019 uint32_t lane : 4;
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrNEON.td3067 // The first element of the structure is placed in the first lane
3068 // of the first first vector, the second element in the first lane
3638 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3639 asmop # "\t$Rt[$lane], [$Rn]",
3652 let Inst{12-10} = lane{2-0};
3653 let Inst{30} = lane{3};
3659 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3660 let Inst{30} = lane{2};
3666 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3667 let Inst{30} = lane{1};
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DAArch64InstrFormats.td1320 // Format AdvSIMD vector load/store Single N-element structure to/from one lane
1326 bits<4> lane;
1360 // to/from one lane
1366 bits<4> lane;
/freebsd-9-stable/sys/dev/bxe/
Dbxe_elink.c4046 uint8_t lane = 0; in elink_get_warpcore_lane() local
4077 lane = (port<<1) + path; in elink_get_warpcore_lane()
4092 lane = path << 1 ; in elink_get_warpcore_lane()
4094 return lane; in elink_get_warpcore_lane()
4370 uint8_t lane = elink_get_warpcore_lane(phy, params); in elink_ext_phy_update_adv_fc() local
4377 lane; in elink_ext_phy_update_adv_fc()
4552 uint16_t lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_restart_AN_KR() local
4554 MDIO_AER_BLOCK_AER_REG, lane); in elink_warpcore_restart_AN_KR()
4565 uint16_t lane, i, cl72_ctrl, an_adv = 0, val; in elink_warpcore_enable_AN_KR() local
4618 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_enable_AN_KR()
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/freebsd-9-stable/contrib/llvm/include/llvm/IR/
DIntrinsicsARM.td411 // Vector load N-element structure to one lane.
413 // lane is assigned), the lane number, and the alignment.
450 // Vector store N-element structure from one lane.
451 // Source operands are: the address, the N vectors, the lane number, and
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1519 unsigned lane = 0; in DecodeVLDSTLanePostInstruction() local
1525 lane = (Q << 3) | S; in DecodeVLDSTLanePostInstruction()
1528 lane = (Q << 2) | (S >> 1); in DecodeVLDSTLanePostInstruction()
1531 lane = (Q << 1) | (S >> 2); in DecodeVLDSTLanePostInstruction()
1534 lane = Q; in DecodeVLDSTLanePostInstruction()
1537 Inst.addOperand(MCOperand::CreateImm(lane)); in DecodeVLDSTLanePostInstruction()
/freebsd-9-stable/usr.sbin/tcpdump/tcpdump/
DMakefile73 print-lane.c \
/freebsd-9-stable/contrib/tcpdump/
DMakefile.in84 print-l2tp.c print-lane.c print-ldp.c print-lldp.c print-llc.c \
153 lane.h \
DINSTALL.txt105 lane.h - ATM LANE definitions
179 print-lane.c - ATM LANE printer routines
/freebsd-9-stable/contrib/libpcap/
Dscanner.l289 lane return LANE;
/freebsd-9-stable/contrib/binutils/gas/config/
Dtc-arm.c1780 int lane = -1; in parse_neon_el_struct_list() local
1839 if (lane == -1) in parse_neon_el_struct_list()
1840 lane = NEON_INTERLEAVE_LANES; in parse_neon_el_struct_list()
1841 else if (lane != NEON_INTERLEAVE_LANES) in parse_neon_el_struct_list()
1878 if (lane == -1) in parse_neon_el_struct_list()
1879 lane = atype.index; in parse_neon_el_struct_list()
1880 else if (lane != atype.index) in parse_neon_el_struct_list()
1886 else if (lane == -1) in parse_neon_el_struct_list()
1887 lane = NEON_INTERLEAVE_LANES; in parse_neon_el_struct_list()
1888 else if (lane != NEON_INTERLEAVE_LANES) in parse_neon_el_struct_list()
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/freebsd-9-stable/contrib/llvm/tools/clang/utils/TableGen/
DNeonEmitter.cpp1582 const std::string &lane) { in SplatLane() argument
1585 s += ", " + lane; in SplatLane()
/freebsd-9-stable/share/misc/
Dpci_vendors4796 8505 PEX 8505 5-lane, 5-port PCI Express Switch
4797 8508 PEX 8508 8-lane, 5-port PCI Express Switch
4798 8509 PEX 8509 8-lane, 8-port PCI Express Switch
4799 8512 PEX 8512 12-lane, 5-port PCI Express Switch
4801 8517 PEX 8517 16-lane, 5-port PCI Express Switch
4802 8518 PEX 8518 16-lane, 5-port PCI Express Switch
4803 8524 PEX 8524 24-lane, 6-port PCI Express Switch
4804 8525 PEX 8525 24-lane, 5-port PCI Express Switch
4806 8533 PEX 8533 32-lane, 6-port PCI Express Switch
4807 8547 PEX 8547 48-lane, 3-port PCI Express Switch
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/freebsd-9-stable/contrib/llvm/tools/clang/include/clang/Basic/
Darm_neon.td1293 // VMUL_LANE_A64 d type implemented using scalar mul lane
1296 // VMUL_LANEQ d type implemented using scalar mul lane
/freebsd-9-stable/games/fortune/datfiles/
Dmurphy672 wrong lane.
1850 lane.

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