Searched refs:imm5 (Results 1 – 9 of 9) sorted by relevance
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 197 // t_addrmode_is4 := reg + imm5 * 4 209 // t_addrmode_is2 := reg + imm5 * 2 221 // t_addrmode_is1 := reg + imm5 582 // Loads: reg/reg and reg/imm5 594 def i : // reg/imm5 600 // Stores: reg/reg and reg/imm5 611 def i : // reg/imm5 903 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 905 "asr", "\t$Rd, $Rm, $imm5", 906 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, [all …]
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| D | ARMInstrFormats.td | 1149 let Inst{10-6} = addr{7-3}; // imm5
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| D | ARMInstrInfo.td | 515 // {4-0} imm5 shift amount. 516 // asr #32 encoded as imm5 == 0.
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| D | ARMInstrThumb2.td | 35 // {4-0} imm5 shift amount.
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| /freebsd-9-stable/contrib/binutils/include/opcode/ |
| D | cr16.h | 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator
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| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|> 238 bits<5> imm5; 245 let Inst{4-0} = imm5;
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| /freebsd-9-stable/contrib/binutils/opcodes/ |
| D | cr16-opc.c | 148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr), 158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
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| D | arm-dis.c | 2094 long imm5; in print_insn_coprocessor() local 2095 imm5 = ((given & 0x100) >> 4) | (given & 0xf); in print_insn_coprocessor() 2096 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); in print_insn_coprocessor()
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| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 557 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5, 571 let Inst{9-5} = imm5;
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