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Searched refs:i8 (Results 1 – 25 of 134) sorted by relevance

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/freebsd-9-stable/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
Dtst.signedkeyspos.d50 @i8["cat", (char)-2] = sum(-2);
51 @i8["dog", (char)-2] = sum(-22);
52 @i8["mouse", (char)-2] = sum(-222);
53 @i8["cat", (char)-1] = sum(-1);
54 @i8["dog", (char)-1] = sum(-11);
55 @i8["mouse", (char)-1] = sum(-111);
56 @i8["cat", (char)0] = sum(0);
57 @i8["dog", (char)0] = sum(10);
58 @i8["mouse", (char)0] = sum(100);
59 @i8["cat", (char)1] = sum(1);
[all …]
Dtst.signedkeys.d95 @i8[(char)-2] = sum(-2);
96 @i8[(char)-1] = sum(-1);
97 @i8[(char)0] = sum(0);
98 @i8[(char)1] = sum(1);
99 @i8[(char)2] = sum(2);
/freebsd-9-stable/contrib/llvm/patches/
Dpatch-r275759-clang-r221170-ppc-vaarg.diff167 -// CHECK: bitcast i8* %{{[a-z.0-9]*}} to %struct.x*
168 -// CHECK: bitcast %struct.x* %t to i8*
169 -// CHECK: bitcast %struct.x* %{{[0-9]+}} to i8*
173 -// CHECK: ptrtoint i8* %{{[a-z.0-9]*}} to i64
175 -// CHECK: inttoptr i64 %{{[0-9]+}} to i8*
176 -// CHECK: bitcast i8* %{{[0-9]+}} to i32*
179 -// CHECK: bitcast i8* %{{[a-z.0-9]+}} to i128*
204 +// CHECK: bitcast i8* %{{[a-z.0-9]*}} to %struct.x*
205 +// CHECK: bitcast %struct.x* %t to i8*
206 +// CHECK: bitcast %struct.x* %{{[0-9]+}} to i8*
[all …]
Dpatch-r263312-llvm-r202930-fix-alloca-esi-clobber.diff164 %struct.foo = type { [88 x i8] }
166 +declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind
167 +declare void @baz(i8*) nounwind
176 -declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind
179 +define void @test2(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind {
180 + call void @bar(i8* %z, %struct.foo* align 4 byval %x)
181 + %dynalloc = alloca i8, i32 %y, align 1
182 + call void @baz(i8* %dynalloc)
191 +define void @test3(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind {
192 + call void @bar(i8* %z, %struct.foo* align 4 byval %x)
[all …]
Dpatch-r252503-arm-transient-stack-alignment.diff35 %ap = alloca i8*, align 4
36 %ap1 = bitcast i8** %ap to i8*
65 %red = alloca [100 x i8], align 1
66 %0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
Dpatch-r262261-llvm-r198480-sparc.diff150 define i8* @frameaddr() nounwind readnone {
162 %0 = tail call i8* @llvm.frameaddress(i32 0)
163 ret i8* %0
177 %0 = tail call i8* @llvm.frameaddress(i32 3)
178 ret i8* %0
187 %0 = tail call i8* @llvm.returnaddress(i32 0)
188 ret i8* %0
211 %0 = tail call i8* @llvm.returnaddress(i32 3)
212 ret i8* %0
Dpatch-r262460-llvm-r202059-sparc.diff33 + llvm::IntegerType *i8 = CGF.Int8Ty;
34 + llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
35 + llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrShiftRotate.td36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>;
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
88 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
92 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
97 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
101 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
107 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
111 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
[all …]
DX86CallingConv.td25 // Scalar values are returned in AX first, then DX. For i8, the ABI
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
30 // for functions that return two i8 values are currently expected to pack the
35 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
89 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
119 CCIfType<[i8, i16], CCPromoteToType<i32>>,
148 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
157 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
223 // Promote i8/i16 arguments to i32.
224 CCIfType<[i8, i16], CCPromoteToType<i32>>,
[all …]
DX86InstrCompiler.td231 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
270 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
272 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
274 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
277 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
279 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
281 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
288 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
292 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
300 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
[all …]
DX86SelectionDAGInfo.cpp109 AVT = MVT::i8; in EmitTargetCodeForMemset()
115 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
125 AVT = MVT::i8; in EmitTargetCodeForMemset()
155 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; in EmitTargetCodeForMemset()
213 AVT = MVT::i8; in EmitTargetCodeForMemcpy()
DX86ISelDAGToDAG.cpp267 return CurDAG->getTargetConstant(Imm, MVT::i8); in getI8Imm()
796 SDValue Eight = DAG.getConstant(8, MVT::i8); in FoldMaskAndShiftToExtract()
800 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8); in FoldMaskAndShiftToExtract()
950 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8); in FoldMaskAndShiftToScale()
952 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8); in FoldMaskAndShiftToScale()
1806 case MVT::i8: in SelectAtomicLoadArith()
1951 LdVT != MVT::i8) in isLoadIncOrDecStore()
2015 if (LdVT == MVT::i8) return X86::DEC8m; in getFusedLdStOpcode()
2021 if (LdVT == MVT::i8) return X86::INC8m; in getFusedLdStOpcode()
2206 CstVT = MVT::i8; in Select()
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp258 case MVT::i8: in SelectLoad()
287 case MVT::i8: in SelectLoad()
317 case MVT::i8: in SelectLoad()
340 case MVT::i8: in SelectLoad()
369 case MVT::i8: in SelectLoad()
392 case MVT::i8: in SelectLoad()
500 case MVT::i8: in SelectLoadVector()
524 case MVT::i8: in SelectLoadVector()
554 case MVT::i8: in SelectLoadVector()
578 case MVT::i8: in SelectLoadVector()
[all …]
/freebsd-9-stable/sys/i386/i386/
Dbpf_jit_machdep.h202 #define ADDib(i8, r32) do { \ argument
205 emitm(&stream, i8, 1); \
222 #define SUBib(i8, r32) do { \ argument
225 emitm(&stream, i8, 1); \
241 #define ANDib(i8, r8) do { \ argument
248 emitm(&stream, i8, 1); \
306 #define SHLib(i8, r32) do { \ argument
309 emitm(&stream, i8, 1); \
319 #define SHRib(i8, r32) do { \ argument
322 emitm(&stream, i8, 1); \
/freebsd-9-stable/sys/amd64/amd64/
Dbpf_jit_machdep.h257 #define ADDib(i8, r32) do { \ argument
260 emitm(&stream, i8, 1); \
277 #define SUBib(i8, r64) do { \ argument
280 emitm(&stream, i8, 1); \
296 #define ANDib(i8, r8) do { \ argument
303 emitm(&stream, i8, 1); \
361 #define SHLib(i8, r32) do { \ argument
364 emitm(&stream, i8, 1); \
374 #define SHRib(i8, r32) do { \ argument
377 emitm(&stream, i8, 1); \
/freebsd-9-stable/contrib/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
95 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
101 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
102 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
109 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
[all …]
DMSP430CallingConv.td16 // i8 are returned in registers R15B, R14B, R13B, R12B
17 CCIfType<[i8], CCAssignToReg<[R15B, R14B, R13B, R12B]>>,
30 // Promote i8 arguments to i16.
31 CCIfType<[i8], CCPromoteToType<i16>>,
DMSP430InstrInfo.td19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
32 SDTCisVT<1, i8>]>;
35 SDTCisVT<3, i8>]>;
90 def cc : Operand<i8> {
297 def def8 : PatLeaf<(i8 GR8:$src), [{
311 [(store (i8 imm:$src), addr:$dst)]>;
329 [(store (i8 (load addr:$src)), addr:$dst)]>;
406 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
418 (i8 (load addr:$src))), addr:$dst),
480 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
[all …]
/freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.td24 def i8 : ValueType<8 , 2>; // 8-bit integer value
42 def v1i8 : ValueType<16, 19>; // 1 x i8 vector value
43 def v2i8 : ValueType<16 , 20>; // 2 x i8 vector value
44 def v4i8 : ValueType<32 , 21>; // 4 x i8 vector value
45 def v8i8 : ValueType<64 , 22>; // 8 x i8 vector value
46 def v16i8 : ValueType<128, 23>; // 16 x i8 vector value
47 def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
48 def v64i8 : ValueType<512, 25>; // 64 x i8 vector value
/freebsd-9-stable/contrib/llvm/lib/Target/Mips/
DMipsCallingConv.td40 // Promote i8/i16 arguments to i32.
41 CCIfType<[i8, i16], CCPromoteToType<i32>>,
74 // Promote i8/i16 arguments to i32.
75 CCIfType<[i8, i16], CCPromoteToType<i32>>,
112 // Promote i8/i16 arguments to i32.
113 CCIfType<[i8, i16], CCPromoteToType<i32>>,
190 // Promote i8/i16 arguments to i32.
191 CCIfType<[i8, i16], CCPromoteToType<i32>>,
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp302 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
303 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
304 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
305 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
333 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
334 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
335 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
336 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
367 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, in getCastInstrCost()
/freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp276 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { in isLoadTypeLegal()
455 case MVT::i8: in PPCEmitLoad()
581 case MVT::i8: in PPCEmitStore()
751 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
770 case MVT::i8: in PPCEmitCmp()
929 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && in SelectIToFP()
951 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { in SelectIToFP()
1090 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1314 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) in finishCall()
1338 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { in finishCall()
[all …]
/freebsd-9-stable/sys/gnu/fs/xfs/
Dxfs_dir2_sf.h56 xfs_dir2_ino8_t i8; member
114 (xfs_intino_t)XFS_GET_DIR_INO8((from)->i8)); in xfs_dir2_sf_get_inumber()
125 XFS_PUT_DIR_INO8(*(from), (to)->i8); in xfs_dir2_sf_put_inumber()
/freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZOperators.td22 [SDTCisVT<0, i8>,
23 SDTCisVT<1, i8>,
28 SDTCisVT<3, i8>,
29 SDTCisVT<4, i8>]>;
40 SDTCisVT<1, i8>]>;
80 [SDTCisVT<0, i8>,
190 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
209 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
224 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
238 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
/freebsd-9-stable/contrib/llvm/lib/Target/XCore/
DXCoreCallingConv.td24 // Promote i8/i16 arguments to i32.
25 CCIfType<[i8, i16], CCPromoteToType<i32>>,

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