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/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMScheduleA9.td82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
DARMScheduleV6.td24 // No operand cycles
109 // Scaled register offset, issues over 2 cycles
122 // Scaled register offset with update, issues over 2 cycles
162 // Scaled register offset, issues over 2 cycles
175 // Scaled register offset with update, issues over 2 cycles
/freebsd-9-stable/contrib/gcc/config/mips/
D24k.md89 ;; mul - delivers result to gpr in 5 cycles
95 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
107 ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
168 ;; load->next use : 2 cycles (Default)
169 ;; load->load base: 3 cycles
170 ;; load->store base: 3 cycles
171 ;; load->prefetch: 3 cycles
176 ;; arith->next use : 1 cycles (Default)
177 ;; arith->load base: 2 cycles
178 ;; arith->store base: 2 cycles
[all …]
Dsb1.md26 ;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for
27 ;; 5 cycles. This is currently not handled because there is no MDMX insn
70 ;; effectively re-issuing the operation every 4 cycles. This means that we
116 ;; A load normally has a latency of zero cycles. In some cases, dependent
189 ;; Load latencies are 3 cycles for one load to another load or store (address
190 ;; only). This is 0 cycles for one load to a store using it as the data
213 ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
265 ;; An alu insn issued on an EX unit has a latency of 5 cycles when the
295 ;; mt{hi,lo} to mul/div is 4 cycles.
302 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
[all …]
D4130.md93 ;; into an integer register will take an additional three cycles, see mflo
103 ;; after 3 cycles.
110 ;; maccs can execute in consecutive cycles without stalling, but it
111 ;; is 3 cycles before the integer destination can be read.
D4k.md91 ;; Repeat rate of 33 cycles.
99 ;; Latency of 32 cycles, but stalls the whole pipeline until complete.
108 ;; Repeat rate of 35 cycles.
/freebsd-9-stable/contrib/gcc/config/sparc/
Dniagara.md79 * FPADD{s,d}: 26 cycles
80 * FPSUB{s,d}: 26 cycles
81 * FABSD: 26 cycles
82 * F{s,d}TO{s,d}: 26 cycles
83 * F{s,d}TO{i,x}: 26 cycles
84 * FSMULD: 29 cycles
112 * FPADD{16,32}: 10 cycles
113 * FPSUB{16,32}: 10 cycles
114 * FALIGNDATA: 10 cycles
/freebsd-9-stable/sys/contrib/octeon-sdk/
Dcvmx-tim.h213 …const uint64_t cycles = cvmx_clock_get_count(CVMX_CLOCK_TIM); /* Get our reference time early fo… in cvmx_tim_add_entry() local
233 current_bucket = ((cycles - cvmx_tim.start_time) in cvmx_tim_add_entry()
235 work_bucket = (((ticks_from_now * cvmx_tim.tick_cycles) + cycles - cvmx_tim.start_time) in cvmx_tim_add_entry()
292 delete_info->commit_cycles = cycles + (ticks_from_now - 2) * cvmx_tim.tick_cycles; in cvmx_tim_add_entry()
317 const uint64_t cycles = cvmx_clock_get_count(CVMX_CLOCK_TIM); in cvmx_tim_delete_entry() local
319 if ((int64_t)(cycles - delete_info->commit_cycles) < 0) in cvmx_tim_delete_entry()
Dcvmx-access-native.h637 static inline void cvmx_wait(uint64_t cycles) in cvmx_wait() argument
639 uint64_t done = cvmx_get_cycle() + cycles; in cvmx_wait()
668 static inline void cvmx_wait_io(uint64_t cycles) in cvmx_wait_io() argument
670 uint64_t done = cvmx_clock_get_count(CVMX_CLOCK_SCLK) + cycles; in cvmx_wait_io()
Dcvmx-access.h195 CVMX_FUNCTION void cvmx_wait(uint64_t cycles);
209 CVMX_FUNCTION void cvmx_wait_io(uint64_t cycles);
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86SchedHaswell.td65 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
66 // cycles after the memory operand.
80 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
103 // The complex ones can only execute on port 1, and they require two cycles on
120 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
DX86SchedSandyBridge.td60 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
61 // cycles after the memory operand.
75 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
98 // The complex ones can only execute on port 1, and they require two cycles on
115 defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
/freebsd-9-stable/contrib/gcc/config/arm/
Darm1026ejs.md60 ;; ALU instructions require three cycles to execute, and use the ALU
65 ;; for several cycles. That case is not modeled here.
81 ;; the shift value in a second cycle. Pretend we take two cycles in
128 ;; output (such as umull) make their results available in two cycles;
159 ;; LSU instructions require six cycles to execute. They use the ALU
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
163 ;; register pre-indexed addressing mode take three cycles EXCEPT for
226 ;; therefore appear to require zero cycles to execute. We assume that
Darm926ejs.md52 ;; ALU instructions require three cycles to execute, and use the ALU
57 ;; for several cycles. That case is not modeled here.
67 ;; the shift value in a second cycle. Pretend we take two cycles in
122 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the
173 ;; therefore appear to require zero cycles to execute. We assume that
Darm1020e.md60 ;; ALU instructions require three cycles to execute, and use the ALU
65 ;; for several cycles. That case is not modeled here.
81 ;; the shift value in a second cycle. Pretend we take two cycles in
128 ;; output (such as umull) make their results available in two cycles;
159 ;; LSU instructions require six cycles to execute. They use the ALU
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
163 ;; register pre-indexed addressing mode take three cycles EXCEPT for
231 ;; therefore appear to require zero cycles to execute. We assume that
321 ;; insns stall for two cycles.
Darm1136jfs.md69 ;; ALU instructions require eight cycles to execute, and use the ALU
74 ;; for several cycles. That case is not modelled here.
90 ;; the shift value in a second cycle. Pretend we take two cycles in
136 ;; The *S variants set the condition flags, which requires three more cycles.
157 ;; Signed and unsigned multiply long results are available across two cycles;
167 ;; The *S variants set the condition flags, which requires three more cycles.
191 ;; cycles.
/freebsd-9-stable/contrib/gcc/
Dipa-inline.c516 cgraph_find_cycles (struct cgraph_node *node, htab_t cycles) in cgraph_find_cycles() argument
523 slot = htab_find_slot (cycles, node, INSERT); in cgraph_find_cycles()
535 cgraph_find_cycles (e->callee, cycles); in cgraph_find_cycles()
545 cgraph_flatten_node (struct cgraph_node *node, htab_t cycles) in cgraph_flatten_node() argument
557 && !htab_find (cycles, e->callee)) in cgraph_flatten_node()
562 cgraph_flatten_node (e->callee, cycles); in cgraph_flatten_node()
961 htab_t cycles; in cgraph_decide_inlining() local
965 cycles = htab_create (7, htab_hash_pointer, htab_eq_pointer, NULL); in cgraph_decide_inlining()
966 cgraph_find_cycles (node, cycles); in cgraph_decide_inlining()
967 cgraph_flatten_node (node, cycles); in cgraph_decide_inlining()
[all …]
/freebsd-9-stable/contrib/llvm/include/llvm/Target/
DTargetItinerary.td48 // cycles should elapse from the start of this stage to the start of
57 class InstrStage<int cycles, list<FuncUnit> units,
60 int Cycles = cycles; // length of stage in machine cycles
62 int TimeInc = timeinc; // cycles till start of next stage
DTargetSchedule.td83 int HighLatency = -1; // Approximation of cycles for "high latency" ops.
84 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
118 // Buffered resources may be held for multiple clock cycles, but the
222 // Optionally, ResourceCycles indicates the number of cycles the
258 class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
259 int Cycles = cycles;
268 // to reduce latency of a prior write by N cycles. A negative advance
277 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
278 : ProcReadAdvance<cycles, writes> {
284 class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,
[all …]
/freebsd-9-stable/sys/kern/
Dkern_poll.c424 int i, cycles; in netisr_poll() local
443 cycles = (residual_burst < poll_each_burst) ? in netisr_poll()
445 residual_burst -= cycles; in netisr_poll()
448 pr[i].handler(pr[i].ifp, arg, cycles); in netisr_poll()
/freebsd-9-stable/crypto/openssl/crypto/ripemd/
DREADME5 off the pace since I only get 1050 cycles, while the best is 1013.
6 I have a few ideas for how to get another 20 or so cycles, but at
/freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/
DPPCSchedule440.td77 // 33 cycles (multiply also calculates its result in IWB). For all
82 // The L1 cache hit latency is four cycles for floating point loads
83 // and three cycles for integer loads.
96 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
98 // loads take 4 cycles (for L1 hit).
/freebsd-9-stable/contrib/ntp/ntpd/
Drefclock_irig.c261 int cycles; /* carrier cycles */ member
696 up->cycles <<= 1; in irig_base()
698 up->cycles |= 1; in irig_base()
699 if ((up->cycles & 0x303c0f03) == 0x300c0300) { in irig_base()
/freebsd-9-stable/contrib/gcc/config/i386/
Dpentium.md219 ;; First two cycles of fmul are not pipelined.
226 ;; but only last 2 cycles with FP ones.
239 ;; Integer instructions. Load/execute/store takes 3 cycles,
240 ;; load/execute 2 cycles and execute only one cycle.
/freebsd-9-stable/contrib/bmake/unit-tests/
Dtest.exp86 make: Graph cycles through `cycle.2.99'
87 make: Graph cycles through `cycle.2.98'
88 make: Graph cycles through `cycle.2.97'

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