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Searched refs:cvmx_warn (Results 1 – 25 of 60) sorted by relevance

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/freebsd-9-stable/sys/contrib/octeon-sdk/
Dcvmx-pexp-defs.h58 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); in CVMX_PEXP_NPEI_BAR1_INDEXX()
69 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n"); in CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
80 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n"); in CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
91 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n"); in CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
102 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n"); in CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
113 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n"); in CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
124 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n"); in CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
135 cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n"); in CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
146 cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n"); in CVMX_PEXP_NPEI_DBG_DATA_FUNC()
157 cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n"); in CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
[all …]
Dcvmx-sli-defs.h60 cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n"); in CVMX_SLI_BIST_STATUS_FUNC()
71 cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset); in CVMX_SLI_CTL_PORTX()
82 cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n"); in CVMX_SLI_CTL_STATUS_FUNC()
93 cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n"); in CVMX_SLI_DATA_OUT_CNT_FUNC()
104 cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n"); in CVMX_SLI_DBG_DATA_FUNC()
115 cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n"); in CVMX_SLI_DBG_SELECT_FUNC()
126 cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset); in CVMX_SLI_DMAX_CNT()
137 cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset); in CVMX_SLI_DMAX_INT_LEVEL()
148 cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset); in CVMX_SLI_DMAX_TIM()
159 cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n"); in CVMX_SLI_INT_ENB_CIU_FUNC()
[all …]
Dcvmx-sriomaintx-defs.h60 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_ASMBLY_ID()
71 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_ASMBLY_INFO()
82 cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_SRIOMAINTX_BAR1_IDXX()
93 cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_BELL_STATUS()
104 cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_COMP_TAG()
115 cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_CORE_ENABLES()
126 cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_DEV_ID()
137 cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_DEV_REV()
148 cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_DST_OPS()
159 cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_ERB_ATTR_CAPT()
[all …]
Dcvmx-uahcx-defs.h60 cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
71 cvmx_warn("CVMX_UAHCX_EHCI_CONFIGFLAG(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_CONFIGFLAG()
82 cvmx_warn("CVMX_UAHCX_EHCI_CTRLDSSEGMENT(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_CTRLDSSEGMENT()
93 cvmx_warn("CVMX_UAHCX_EHCI_FRINDEX(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_FRINDEX()
104 cvmx_warn("CVMX_UAHCX_EHCI_HCCAPBASE(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_HCCAPBASE()
115 cvmx_warn("CVMX_UAHCX_EHCI_HCCPARAMS(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_HCCPARAMS()
126 cvmx_warn("CVMX_UAHCX_EHCI_HCSPARAMS(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_HCSPARAMS()
137 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG00(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_INSNREG00()
148 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG03(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_INSNREG03()
159 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG04(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_INSNREG04()
[all …]
Dcvmx-pcmx-defs.h62 cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_DMA_CFG()
75 cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_INT_ENA()
88 cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_INT_SUM()
101 cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXADDR()
114 cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXCNT()
127 cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXMSK0()
140 cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXMSK1()
153 cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXMSK2()
166 cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXMSK3()
179 cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset); in CVMX_PCMX_RXMSK4()
[all …]
Dcvmx-rad-defs.h60 cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n"); in CVMX_RAD_MEM_DEBUG0_FUNC()
71 cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n"); in CVMX_RAD_MEM_DEBUG1_FUNC()
82 cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n"); in CVMX_RAD_MEM_DEBUG2_FUNC()
93 cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n"); in CVMX_RAD_REG_BIST_RESULT_FUNC()
104 cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n"); in CVMX_RAD_REG_CMD_BUF_FUNC()
115 cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n"); in CVMX_RAD_REG_CTL_FUNC()
126 cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n"); in CVMX_RAD_REG_DEBUG0_FUNC()
137 cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n"); in CVMX_RAD_REG_DEBUG1_FUNC()
148 cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n"); in CVMX_RAD_REG_DEBUG10_FUNC()
159 cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n"); in CVMX_RAD_REG_DEBUG11_FUNC()
[all …]
Dcvmx-dpi-defs.h60 cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n"); in CVMX_DPI_BIST_STATUS_FUNC()
71 cvmx_warn("CVMX_DPI_CTL not supported on this chip\n"); in CVMX_DPI_CTL_FUNC()
82 cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMAX_COUNTS()
93 cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMAX_DBELL()
104 cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMAX_IBUFF_SADDR()
115 cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMAX_NADDR()
126 cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMAX_REQBNK0()
137 cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMAX_REQBNK1()
148 cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n"); in CVMX_DPI_DMA_CONTROL_FUNC()
159 cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset); in CVMX_DPI_DMA_ENGX_EN()
[all …]
Dcvmx-dfa-defs.h60 cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n"); in CVMX_DFA_BIST0_FUNC()
71 cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n"); in CVMX_DFA_BIST1_FUNC()
82 cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n"); in CVMX_DFA_BST0_FUNC()
93 cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n"); in CVMX_DFA_BST1_FUNC()
104 cvmx_warn("CVMX_DFA_CFG not supported on this chip\n"); in CVMX_DFA_CFG_FUNC()
115 cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n"); in CVMX_DFA_CONFIG_FUNC()
126 cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n"); in CVMX_DFA_CONTROL_FUNC()
137 cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n"); in CVMX_DFA_DBELL_FUNC()
148 cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n"); in CVMX_DFA_DDR2_ADDR_FUNC()
159 cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n"); in CVMX_DFA_DDR2_BUS_FUNC()
[all …]
Dcvmx-pcieepx-defs.h62 cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG000()
75 cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG001()
88 cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG002()
101 cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG003()
114 cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG004()
127 cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG004_MASK()
140 cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG005()
153 cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG005_MASK()
166 cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG006()
179 cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG006_MASK()
[all …]
Dcvmx-pciercx-defs.h62 cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG000()
75 cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG001()
88 cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG002()
101 cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG003()
114 cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG004()
127 cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG005()
140 cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG006()
153 cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG007()
166 cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG008()
179 cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG009()
[all …]
Dcvmx-asxx-defs.h62 cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_GMII_RX_CLK_SET()
75 cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_GMII_RX_DAT_SET()
90 cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_INT_EN()
105 cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_INT_REG()
117 cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_MII_RX_DAT_SET()
132 cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_PRT_LOOP()
144 cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_RLD_BYPASS()
156 cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_RLD_BYPASS_SETTING()
168 cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_RLD_COMP()
180 cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_RLD_DATA_DRV()
[all …]
Dcvmx-agl-defs.h60 cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n"); in CVMX_AGL_GMX_BAD_REG_FUNC()
71 cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n"); in CVMX_AGL_GMX_BIST_FUNC()
82 cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n"); in CVMX_AGL_GMX_DRV_CTL_FUNC()
93 cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n"); in CVMX_AGL_GMX_INF_MODE_FUNC()
106 cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset); in CVMX_AGL_GMX_PRTX_CFG()
119 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset); in CVMX_AGL_GMX_RXX_ADR_CAM0()
132 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset); in CVMX_AGL_GMX_RXX_ADR_CAM1()
145 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset); in CVMX_AGL_GMX_RXX_ADR_CAM2()
158 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset); in CVMX_AGL_GMX_RXX_ADR_CAM3()
171 cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset); in CVMX_AGL_GMX_RXX_ADR_CAM4()
[all …]
Dcvmx-stxx-defs.h61 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_ARB_CTL()
73 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_BCKPRS_CNT()
85 cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_COM_CTL()
97 cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_DIP_CNT()
109 cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_IGN_CAL()
121 cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_INT_MSK()
133 cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_INT_REG()
145 cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_INT_SYNC()
157 cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_MIN_BST()
169 cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_STXX_SPI4_CALX()
[all …]
Dcvmx-led-defs.h60 cvmx_warn("CVMX_LED_BLINK not supported on this chip\n"); in CVMX_LED_BLINK_FUNC()
71 cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n"); in CVMX_LED_CLK_PHASE_FUNC()
82 cvmx_warn("CVMX_LED_CYLON not supported on this chip\n"); in CVMX_LED_CYLON_FUNC()
93 cvmx_warn("CVMX_LED_DBG not supported on this chip\n"); in CVMX_LED_DBG_FUNC()
104 cvmx_warn("CVMX_LED_EN not supported on this chip\n"); in CVMX_LED_EN_FUNC()
115 cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n"); in CVMX_LED_POLARITY_FUNC()
126 cvmx_warn("CVMX_LED_PRT not supported on this chip\n"); in CVMX_LED_PRT_FUNC()
137 cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n"); in CVMX_LED_PRT_FMT_FUNC()
150 cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset); in CVMX_LED_PRT_STATUSX()
163 cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset); in CVMX_LED_UDD_CNTX()
[all …]
Dcvmx-l2c-defs.h60 cvmx_warn("CVMX_L2C_BIG_CTL not supported on this chip\n"); in CVMX_L2C_BIG_CTL_FUNC()
71 cvmx_warn("CVMX_L2C_BST not supported on this chip\n"); in CVMX_L2C_BST_FUNC()
82 cvmx_warn("CVMX_L2C_BST0 not supported on this chip\n"); in CVMX_L2C_BST0_FUNC()
93 cvmx_warn("CVMX_L2C_BST1 not supported on this chip\n"); in CVMX_L2C_BST1_FUNC()
104 cvmx_warn("CVMX_L2C_BST2 not supported on this chip\n"); in CVMX_L2C_BST2_FUNC()
115 cvmx_warn("CVMX_L2C_BST_MEMX(%lu) is invalid on this chip\n", block_id); in CVMX_L2C_BST_MEMX()
126 cvmx_warn("CVMX_L2C_BST_TDTX(%lu) is invalid on this chip\n", block_id); in CVMX_L2C_BST_TDTX()
137 cvmx_warn("CVMX_L2C_BST_TTGX(%lu) is invalid on this chip\n", block_id); in CVMX_L2C_BST_TTGX()
148 cvmx_warn("CVMX_L2C_CFG not supported on this chip\n"); in CVMX_L2C_CFG_FUNC()
159 cvmx_warn("CVMX_L2C_COP0_MAPX(%lu) is invalid on this chip\n", offset); in CVMX_L2C_COP0_MAPX()
[all …]
Dcvmx-dfm-defs.h60 cvmx_warn("CVMX_DFM_CHAR_CTL not supported on this chip\n"); in CVMX_DFM_CHAR_CTL_FUNC()
71 cvmx_warn("CVMX_DFM_CHAR_MASK0 not supported on this chip\n"); in CVMX_DFM_CHAR_MASK0_FUNC()
82 cvmx_warn("CVMX_DFM_CHAR_MASK2 not supported on this chip\n"); in CVMX_DFM_CHAR_MASK2_FUNC()
93 cvmx_warn("CVMX_DFM_CHAR_MASK4 not supported on this chip\n"); in CVMX_DFM_CHAR_MASK4_FUNC()
104 cvmx_warn("CVMX_DFM_COMP_CTL2 not supported on this chip\n"); in CVMX_DFM_COMP_CTL2_FUNC()
115 cvmx_warn("CVMX_DFM_CONFIG not supported on this chip\n"); in CVMX_DFM_CONFIG_FUNC()
126 cvmx_warn("CVMX_DFM_CONTROL not supported on this chip\n"); in CVMX_DFM_CONTROL_FUNC()
137 cvmx_warn("CVMX_DFM_DLL_CTL2 not supported on this chip\n"); in CVMX_DFM_DLL_CTL2_FUNC()
148 cvmx_warn("CVMX_DFM_DLL_CTL3 not supported on this chip\n"); in CVMX_DFM_DLL_CTL3_FUNC()
159 cvmx_warn("CVMX_DFM_FCLK_CNT not supported on this chip\n"); in CVMX_DFM_FCLK_CNT_FUNC()
[all …]
Dcvmx-sriox-defs.h60 cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_ACC_CTRL()
71 cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_ASMBLY_ID()
82 cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_ASMBLY_INFO()
93 cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_BELL_RESP_CTRL()
104 cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_BIST_STATUS()
115 cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_IMSG_CTRL()
126 cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_SRIOX_IMSG_INST_HDRX()
137 cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_SRIOX_IMSG_QOS_GRPX()
148 cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_SRIOX_IMSG_STATUSX()
159 cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_IMSG_VPORT_THR()
[all …]
Dcvmx-npi-defs.h68 cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset); in CVMX_NPI_BASE_ADDR_INPUTX()
87 cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset); in CVMX_NPI_BASE_ADDR_OUTPUTX()
98 cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n"); in CVMX_NPI_BIST_STATUS_FUNC()
117 cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset); in CVMX_NPI_BUFF_SIZE_OUTPUTX()
128 cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n"); in CVMX_NPI_COMP_CTL_FUNC()
139 cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n"); in CVMX_NPI_CTL_STATUS_FUNC()
150 cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n"); in CVMX_NPI_DBG_SELECT_FUNC()
161 cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n"); in CVMX_NPI_DMA_CONTROL_FUNC()
172 cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n"); in CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
183 cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n"); in CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
[all …]
Dcvmx-pemx-defs.h60 cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_PEMX_BAR1_INDEXX()
71 cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_BAR_CTL()
82 cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_BIST_STATUS()
93 cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_BIST_STATUS2()
104 cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_CFG_RD()
115 cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_CFG_WR()
126 cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_CPL_LUT_VALID()
137 cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_CTL_STATUS()
148 cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_DBG_INFO()
159 cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id); in CVMX_PEMX_DBG_INFO_EN()
[all …]
Dcvmx-mio-defs.h61 cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n"); in CVMX_MIO_BOOT_COMP_FUNC()
74 cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_DMA_CFGX()
87 cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_DMA_INTX()
100 cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_DMA_INT_ENX()
113 cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_DMA_TIMX()
134 cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_LOC_CFGX()
146 cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n"); in CVMX_MIO_BOOT_PIN_DEFS_FUNC()
164 cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_REG_CFGX()
182 cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_BOOT_REG_TIMX()
198 cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset); in CVMX_MIO_FUS_BNK_DATX()
[all …]
Dcvmx-uctlx-defs.h60 cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_BIST_STATUS()
71 cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_CLK_RST_CTL()
82 cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_EHCI_CTL()
93 cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_EHCI_FLA()
104 cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_ERTO_CTL()
115 cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_IF_ENA()
126 cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_INT_ENA()
137 cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_INT_REG()
148 cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_OHCI_CTL()
159 cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_ORTO_CTL()
[all …]
Dcvmx-npei-defs.h61 cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); in CVMX_NPEI_BAR1_INDEXX()
72 cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n"); in CVMX_NPEI_BIST_STATUS_FUNC()
83 cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n"); in CVMX_NPEI_BIST_STATUS2_FUNC()
94 cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n"); in CVMX_NPEI_CTL_PORT0_FUNC()
105 cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n"); in CVMX_NPEI_CTL_PORT1_FUNC()
116 cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n"); in CVMX_NPEI_CTL_STATUS_FUNC()
127 cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n"); in CVMX_NPEI_CTL_STATUS2_FUNC()
138 cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n"); in CVMX_NPEI_DATA_OUT_CNT_FUNC()
149 cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n"); in CVMX_NPEI_DBG_DATA_FUNC()
160 cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n"); in CVMX_NPEI_DBG_SELECT_FUNC()
[all …]
Dcvmx-spxx-defs.h61 cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_BCKPRS_CNT()
73 cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_BIST_STAT()
85 cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_CLK_CTL()
97 cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_CLK_STAT()
109 cvmx_warn("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_DBG_DESKEW_CTL()
121 cvmx_warn("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_DBG_DESKEW_STATE()
133 cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_DRV_CTL()
145 cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_ERR_CTL()
157 cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_INT_DAT()
169 cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_INT_MSK()
[all …]
Dcvmx-pci-defs.h64 cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); in CVMX_PCI_BAR1_INDEXX()
75 cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n"); in CVMX_PCI_BIST_REG_FUNC()
86 cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n"); in CVMX_PCI_CFG00_FUNC()
97 cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n"); in CVMX_PCI_CFG01_FUNC()
108 cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n"); in CVMX_PCI_CFG02_FUNC()
119 cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n"); in CVMX_PCI_CFG03_FUNC()
130 cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n"); in CVMX_PCI_CFG04_FUNC()
141 cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n"); in CVMX_PCI_CFG05_FUNC()
152 cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n"); in CVMX_PCI_CFG06_FUNC()
163 cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n"); in CVMX_PCI_CFG07_FUNC()
[all …]
Dcvmx-usbcx-defs.h64 cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id); in CVMX_USBCX_DAINT()
79 cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id); in CVMX_USBCX_DAINTMSK()
94 cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id); in CVMX_USBCX_DCFG()
109 cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id); in CVMX_USBCX_DCTL()
124 cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_USBCX_DIEPCTLX()
139 cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_USBCX_DIEPINTX()
154 cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id); in CVMX_USBCX_DIEPMSK()
169 cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_USBCX_DIEPTSIZX()
184 cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_USBCX_DOEPCTLX()
199 cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_USBCX_DOEPINTX()
[all …]

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