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Searched refs:control_1 (Results 1 – 10 of 10) sorted by relevance

/freebsd-9-stable/sys/dev/nxge/include/
Dxgehal-ring.h56 #define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF) argument
57 #define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF)) argument
66 #define XGE_HAL_RXD_GET_T_CODE(control_1) \ argument
67 ((control_1 & XGE_HAL_RXD_T_CODE)>>48)
68 #define XGE_HAL_RXD_SET_T_CODE(control_1, val) \ argument
69 (control_1 |= (((u64)val & 0xF) << 48))
73 #define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ argument
74 (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
75 #define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ argument
76 (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32)
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Dxgehal-fifo.h98 u64 control_1; member
/freebsd-9-stable/sys/dev/nxge/xgehal/
Dxgehal-ring-fp.c167 rxdp->control_1 = rxdp->control_2 = 0; in xge_hal_ring_dtr_reserve()
197 ext_info->l3_cksum = XGE_HAL_RXD_GET_L3_CKSUM(rxdp->control_1); in xge_hal_ring_dtr_info_get()
198 ext_info->l4_cksum = XGE_HAL_RXD_GET_L4_CKSUM(rxdp->control_1); in xge_hal_ring_dtr_info_get()
199 ext_info->frame = XGE_HAL_RXD_GET_FRAME_TYPE(rxdp->control_1); in xge_hal_ring_dtr_info_get()
200 ext_info->proto = XGE_HAL_RXD_GET_FRAME_PROTO(rxdp->control_1); in xge_hal_ring_dtr_info_get()
207 ext_info->rth_it_hit = XGE_HAL_RXD_GET_RTH_IT_HIT(rxdp->control_1); in xge_hal_ring_dtr_info_get()
209 XGE_HAL_RXD_GET_RTH_SPDM_HIT(rxdp->control_1); in xge_hal_ring_dtr_info_get()
211 XGE_HAL_RXD_GET_RTH_HASH_TYPE(rxdp->control_1); in xge_hal_ring_dtr_info_get()
236 ext_info->l3_cksum = XGE_HAL_RXD_GET_L3_CKSUM(rxdp->control_1); in xge_hal_ring_dtr_info_nb_get()
237 ext_info->l4_cksum = XGE_HAL_RXD_GET_L4_CKSUM(rxdp->control_1); in xge_hal_ring_dtr_info_nb_get()
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Dxgehal-fifo-fp.c62 txdp->control_1 |= XGE_HAL_TXD_LIST_OWN_XENA; in __hal_fifo_dtr_post_single()
66 XGE_HAL_SET_TXD_T_CODE(txdp->control_1, XGE_HAL_TXD_T_CODE_UNUSED_5); in __hal_fifo_dtr_post_single()
91 if (txdp->control_1 & XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO)) { in __hal_fifo_dtr_post_single()
123 txdp->control_1, txdp->control_2, txdp->buffer_pointer, in __hal_fifo_dtr_post_single()
367 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_reserve_many()
449 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_reserve()
518 txdp_first->control_1 |= XGE_HAL_TXD_GATHER_CODE_FIRST; in xge_hal_fifo_dtr_post()
522 txdp_last->control_1 |= XGE_HAL_TXD_GATHER_CODE_LAST; in xge_hal_fifo_dtr_post()
572 txdp_first->control_1 |= XGE_HAL_TXD_GATHER_CODE_FIRST; in xge_hal_fifo_dtr_post_many()
578 txdp_last->control_1 |= XGE_HAL_TXD_GATHER_CODE_LAST; in xge_hal_fifo_dtr_post_many()
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Dxgehal-device.c5658 txdp->control_1, txdp->control_2, txdp->buffer_pointer, in xge_hal_device_handle_tcode()
5697 ":"XGE_OS_LLXFMT, rxdp->control_1, in xge_hal_device_handle_tcode()
/freebsd-9-stable/sys/dev/vxge/include/
Dvxgehal-ll.h633 u64 control_1; member
900 u64 control_1; member
1204 u64 control_1; member
1446 rxdp->control_1 &= ~VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK; in vxge_hal_ring_rxd_1b_set()
1447 rxdp->control_1 |= VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(size); in vxge_hal_ring_rxd_1b_set()
1475 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK); in vxge_hal_ring_rxd_3b_set()
1476 rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(sizes[0]); in vxge_hal_ring_rxd_3b_set()
1478 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK); in vxge_hal_ring_rxd_3b_set()
1479 rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(sizes[1]); in vxge_hal_ring_rxd_3b_set()
1481 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK); in vxge_hal_ring_rxd_3b_set()
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/freebsd-9-stable/sys/dev/vxge/vxgehal/
Dvxgehal-ring.c980 rxdp->control_0 = rxdp->control_1 = 0; in vxge_hal_ring_rxd_reserve()
1128 rxdp->control_1 |= VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER; in vxge_hal_ring_rxd_post_post()
1195 rxdp->control_1 |= VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER; in vxge_hal_ring_rxd_post()
1389 (!(rxdp->control_1 & in vxge_hal_ring_is_next_rxd_completed()
1456 u64 own, control_0, control_1; in vxge_hal_ring_rxd_next_completed() local
1510 control_1 = rxdp->control_1; in vxge_hal_ring_rxd_next_completed()
1514 if ((!own && !(control_1 & VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER)) || in vxge_hal_ring_rxd_next_completed()
1544 rxdp->control_1); in vxge_hal_ring_rxd_next_completed()
1549 rxdp->control_1) + in vxge_hal_ring_rxd_next_completed()
1551 rxdp->control_1) + in vxge_hal_ring_rxd_next_completed()
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Dvxgehal-doorbells.h109 u64 control_1;
186 u64 control_1;
Dvxgehal-fifo.c617 ((vxge_hal_fifo_txd_t *) txdlh)->control_1)) ? in vxge_hal_fifo_doorbell_reset()
890 txdp->control_0 = txdp->control_1 = 0; in vxge_hal_fifo_txdl_reserve()
1308 txdp->control_1 |= fifo->interrupt_type; in vxge_hal_fifo_txdl_new_frame_set()
1309 txdp->control_1 |= VXGE_HAL_FIFO_TXD_INT_NUMBER( in vxge_hal_fifo_txdl_new_frame_set()
1312 txdp->control_1 |= VXGE_HAL_FIFO_TXD_NO_BW_LIMIT; in vxge_hal_fifo_txdl_new_frame_set()
1378 txdp_first->control_1 |= in vxge_hal_fifo_txdl_post()
1380 txdp_first->control_1 |= fifo->interrupt_type; in vxge_hal_fifo_txdl_post()
1383 txdp_first->control_1 |= VXGE_HAL_FIFO_TXD_NO_BW_LIMIT; in vxge_hal_fifo_txdl_post()
1429 txdp_first->control_0, txdp_first->control_1, in vxge_hal_fifo_txdl_post()
Dvxgehal-mgmtaux.c2875 rxd1->control_1, rxd1->buffer0_ptr); in vxge_hal_aux_vpath_ring_dump()
2887 rxd3->control_1, rxd3->buffer0_ptr, in vxge_hal_aux_vpath_ring_dump()
2903 rxd5->control_1, rxd5->control_2, in vxge_hal_aux_vpath_ring_dump()
2967 txd->control_0, txd->control_1, in vxge_hal_aux_vpath_fifo_dump()