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Searched refs:cfg1 (Results 1 – 17 of 17) sorted by relevance

/freebsd-9-stable/sys/mips/mips/
Dcpu.c77 u_int32_t cfg1; in mips_get_identity() local
103 cfg1 = mips_rd_config1(); in mips_get_identity()
106 ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; in mips_get_identity()
121 tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; in mips_get_identity()
124 cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; in mips_get_identity()
126 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); in mips_get_identity()
131 tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; in mips_get_identity()
135 (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; in mips_get_identity()
137 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); in mips_get_identity()
194 uint32_t cfg0, cfg1, cfg2, cfg3; in cpu_identify() local
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/freebsd-9-stable/sys/dev/ata/chipsets/
Data-nvidia.c185 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
186 ((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) || in ata_nvidia_probe()
202 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
213 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
223 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
292 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
293 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
297 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
307 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
Data-highpoint.c97 if (idx->cfg1 == HPT_374) { in ata_highpoint_probe()
131 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
154 if (ctlr->chip->cfg1 == HPT_366) in ata_highpoint_ch_attach()
194 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
206 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { in ata_highpoint_check_80pin()
Data-sis.c125 id[0].cfg1 = SIS_133NEW; in ata_sis_probe()
139 id[0].cfg1 = SIS_133OLD; in ata_sis_probe()
142 id[0].cfg1 = SIS_100NEW; in ata_sis_probe()
169 switch (ctlr->chip->cfg1) { in ata_sis_chipinit()
249 if (ctlr->chip->cfg1 == SIS_133NEW) { in ata_sis_setmode()
263 switch (ctlr->chip->cfg1) { in ata_sis_setmode()
Data-amd.c98 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
123 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
153 if (ctlr->chip->cfg1 & AMD_CABLE) in ata_amd_ch_attach()
Data-acard.c119 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipinit()
145 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipdeinit()
175 if (ctlr->chip->cfg1 == ATP_OLD && in ata_acard_status()
Data-serverworks.c133 if (ctlr->chip->cfg1 == SWKS_MIO) { in ata_serverworks_chipinit()
148 else if (ctlr->chip->cfg1 == SWKS_33) { in ata_serverworks_chipinit()
168 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); in ata_serverworks_chipinit()
390 if (ctlr->chip->cfg1 != SWKS_33) { in ata_serverworks_setmode()
Data-intel.c334 if ((ctlr->chip->cfg1 & INTEL_AHCI) && in ata_intel_chipinit()
340 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_chipinit()
362 (ctlr->chip->cfg1 & INTEL_ICH5)) in ata_intel_chipinit()
409 if (ctlr->chip->cfg1 & INTEL_ICH5) { in ata_intel_ch_attach()
425 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { in ata_intel_ch_attach()
447 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { in ata_intel_ch_attach()
451 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_ch_attach()
502 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) in ata_intel_reset()
Data-via.c257 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
259 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
261 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
371 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); in ata_via_old_setmode()
Data-ati.c110 switch (ctlr->chip->cfg1) { in ata_ati_probe()
140 if (ctlr->chip->cfg1 == ATI_AHCI) { in ata_ati_chipinit()
Data-jmicron.c120 if (ctlr->chip->cfg1) { in ata_jmicron_chipinit()
Data-marvell.c155 if (ctlr->chip->cfg1) { in ata_marvell_chipinit()
234 ctlr->channels = ctlr->chip->cfg1; in ata_marvell_edma_chipinit()
238 if (ctlr->chip->cfg1 > 4) in ata_marvell_edma_chipinit()
Data-promise.c225 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
376 if (ctlr->chip->cfg1 == PR_NEW) { in ata_promise_ch_attach()
481 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
512 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
514 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_promise_setmode()
Data-acerlabs.c115 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
Data-siliconimage.c128 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
/freebsd-9-stable/sys/dev/et/
Dif_et.c504 uint32_t cfg1, cfg2, ctrl; in et_miibus_statchg() local
537 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
538 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | in et_miibus_statchg()
569 cfg1 |= ET_MAC_CFG1_TXFLOW; in et_miibus_statchg()
572 cfg1 |= ET_MAC_CFG1_RXFLOW; in et_miibus_statchg()
578 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; in et_miibus_statchg()
579 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); in et_miibus_statchg()
584 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
585 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == in et_miibus_statchg()
/freebsd-9-stable/sys/dev/ata/
Data-pci.h33 int cfg1; member