1 /*
2 * Copyright (c) 2014, LSI Corp.
3 * All rights reserved.
4 * Authors: Marian Choy
5 * Support: freebsdraid@lsi.com
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of the <ORGANIZATION> nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * The views and conclusions contained in the software and documentation
35 * are those of the authors and should not be interpreted as representing
36 * official policies,either expressed or implied, of the FreeBSD Project.
37 *
38 * Send feedback to: <megaraidfbsd@lsi.com>
39 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
40 * ATTN: MegaRaid FreeBSD
41 *
42 */
43
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD: stable/9/sys/dev/mrsas/mrsas.h 273912 2014-10-31 18:18:04Z hselasky $");
46
47 #ifndef MRSAS_H
48 #define MRSAS_H
49
50 #include <sys/param.h> /* defines used in kernel.h */
51 #include <sys/module.h>
52 #include <sys/systm.h>
53 #include <sys/proc.h>
54 #include <sys/errno.h>
55 #include <sys/kernel.h> /* types used in module initialization */
56 #include <sys/conf.h> /* cdevsw struct */
57 #include <sys/uio.h> /* uio struct */
58 #include <sys/malloc.h>
59 #include <sys/bus.h> /* structs, prototypes for pci bus stuff */
60
61 #include <machine/bus.h>
62 #include <sys/rman.h>
63 #include <machine/resource.h>
64 #include <machine/atomic.h>
65
66 #include <dev/pci/pcivar.h> /* For pci_get macros! */
67 #include <dev/pci/pcireg.h>
68
69 #include <sys/types.h>
70 #include <sys/sysctl.h>
71 #include <sys/stat.h>
72 #include <sys/taskqueue.h>
73 #include <sys/poll.h>
74 #include <sys/selinfo.h>
75
76 /*
77 * Device IDs and PCI
78 */
79 #define MRSAS_TBOLT 0x005b
80 #define MRSAS_INVADER 0x005d
81 #define MRSAS_FURY 0x005f
82 #define MRSAS_PCI_BAR0 0x10
83 #define MRSAS_PCI_BAR1 0x14
84 #define MRSAS_PCI_BAR2 0x1C
85
86 /*
87 * Firmware State Defines
88 */
89 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF
90 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000
91 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1
92
93 /*
94 * Message Frame Defines
95 */
96 #define MRSAS_SENSE_LEN 96
97 #define MRSAS_FUSION_MAX_RESET_TRIES 3
98
99 /*
100 * Miscellaneous Defines
101 */
102 #define BYTE_ALIGNMENT 1
103 #define MRSAS_MAX_NAME_LENGTH 32
104 #define MRSAS_VERSION "06.704.01.00-fbsd"
105 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
106 #define MRSAS_DEFAULT_TIMEOUT 0x14 //temp
107 #define DONE 0
108 #define MRSAS_PAGE_SIZE 4096
109 #define MRSAS_RESET_NOTICE_INTERVAL 5
110 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */
111 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */
112 #define THRESHOLD_REPLY_COUNT 50
113
114 /*
115 Boolean types
116 */
117 #if (__FreeBSD_version < 901000)
118 typedef enum _boolean { false, true } boolean;
119 #endif
120 enum err { SUCCESS, FAIL };
121
122 MALLOC_DECLARE(M_MRSAS);
123 SYSCTL_DECL(_hw_mrsas);
124
125 #define MRSAS_INFO (1 << 0)
126 #define MRSAS_TRACE (1 << 1)
127 #define MRSAS_FAULT (1 << 2)
128 #define MRSAS_OCR (1 << 3)
129 #define MRSAS_TOUT MRSAS_OCR
130 #define MRSAS_AEN (1 << 4)
131 #define MRSAS_PRL11 (1 << 5)
132
133 #define mrsas_dprint(sc, level, msg, args...) \
134 do { \
135 if (sc->mrsas_debug & level) \
136 device_printf(sc->mrsas_dev, msg, ##args); \
137 } while (0)
138
139
140 /****************************************************************************
141 * Raid Context structure which describes MegaRAID specific IO Paramenters
142 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
143 ****************************************************************************/
144
145 typedef struct _RAID_CONTEXT {
146 u_int8_t Type:4; // 0x00
147 u_int8_t nseg:4; // 0x00
148 u_int8_t resvd0; // 0x01
149 u_int16_t timeoutValue; // 0x02 -0x03
150 u_int8_t regLockFlags; // 0x04
151 u_int8_t resvd1; // 0x05
152 u_int16_t VirtualDiskTgtId; // 0x06 -0x07
153 u_int64_t regLockRowLBA; // 0x08 - 0x0F
154 u_int32_t regLockLength; // 0x10 - 0x13
155 u_int16_t nextLMId; // 0x14 - 0x15
156 u_int8_t exStatus; // 0x16
157 u_int8_t status; // 0x17 status
158 u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0]
159 u_int8_t numSGE; // 0x19 numSge; not including chain entries
160 u_int16_t configSeqNum; // 0x1A -0x1B
161 u_int8_t spanArm; // 0x1C span[7:5], arm[4:0]
162 u_int8_t resvd2[3]; // 0x1D-0x1f
163 } RAID_CONTEXT;
164
165
166 /*************************************************************************
167 * MPI2 Defines
168 ************************************************************************/
169
170 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
171 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
172 #define MPI2_VERSION_MAJOR (0x02)
173 #define MPI2_VERSION_MINOR (0x00)
174 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
175 #define MPI2_VERSION_MAJOR_SHIFT (8)
176 #define MPI2_VERSION_MINOR_MASK (0x00FF)
177 #define MPI2_VERSION_MINOR_SHIFT (0)
178 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
179 MPI2_VERSION_MINOR)
180 #define MPI2_HEADER_VERSION_UNIT (0x10)
181 #define MPI2_HEADER_VERSION_DEV (0x00)
182 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
183 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
184 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
185 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
186 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
187 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
188 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
189 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
190 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
191 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
192 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
193 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
194 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
195 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
196 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
197 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
198 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
199 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
200 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
201 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
202 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
203 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
204 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
205 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
206 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
207 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
208 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
209 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
210 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
211 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
212
213 #ifndef MPI2_POINTER
214 #define MPI2_POINTER *
215 #endif
216
217
218 /***************************************
219 * MPI2 Structures
220 ***************************************/
221
222 typedef struct _MPI25_IEEE_SGE_CHAIN64
223 {
224 u_int64_t Address;
225 u_int32_t Length;
226 u_int16_t Reserved1;
227 u_int8_t NextChainOffset;
228 u_int8_t Flags;
229 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
230 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
231
232 typedef struct _MPI2_SGE_SIMPLE_UNION
233 {
234 u_int32_t FlagsLength;
235 union
236 {
237 u_int32_t Address32;
238 u_int64_t Address64;
239 } u;
240 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
241 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
242
243 typedef struct
244 {
245 u_int8_t CDB[20]; /* 0x00 */
246 u_int32_t PrimaryReferenceTag; /* 0x14 */
247 u_int16_t PrimaryApplicationTag; /* 0x18 */
248 u_int16_t PrimaryApplicationTagMask; /* 0x1A */
249 u_int32_t TransferLength; /* 0x1C */
250 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
251 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
252
253 typedef struct _MPI2_SGE_CHAIN_UNION
254 {
255 u_int16_t Length;
256 u_int8_t NextChainOffset;
257 u_int8_t Flags;
258 union
259 {
260 u_int32_t Address32;
261 u_int64_t Address64;
262 } u;
263 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
264 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
265
266 typedef struct _MPI2_IEEE_SGE_SIMPLE32
267 {
268 u_int32_t Address;
269 u_int32_t FlagsLength;
270 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
271 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
272 typedef struct _MPI2_IEEE_SGE_SIMPLE64
273 {
274 u_int64_t Address;
275 u_int32_t Length;
276 u_int16_t Reserved1;
277 u_int8_t Reserved2;
278 u_int8_t Flags;
279 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
280 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
281
282 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
283 {
284 MPI2_IEEE_SGE_SIMPLE32 Simple32;
285 MPI2_IEEE_SGE_SIMPLE64 Simple64;
286 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
287 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
288
289 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
290 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
291
292 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
293 {
294 MPI2_IEEE_SGE_CHAIN32 Chain32;
295 MPI2_IEEE_SGE_CHAIN64 Chain64;
296 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
297 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
298
299 typedef union _MPI2_SGE_IO_UNION
300 {
301 MPI2_SGE_SIMPLE_UNION MpiSimple;
302 MPI2_SGE_CHAIN_UNION MpiChain;
303 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
304 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
305 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
306 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
307
308 typedef union
309 {
310 u_int8_t CDB32[32];
311 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
312 MPI2_SGE_SIMPLE_UNION SGE;
313 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
314 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
315
316 /*
317 * RAID SCSI IO Request Message
318 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
319 */
320 typedef struct _MPI2_RAID_SCSI_IO_REQUEST
321 {
322 u_int16_t DevHandle; /* 0x00 */
323 u_int8_t ChainOffset; /* 0x02 */
324 u_int8_t Function; /* 0x03 */
325 u_int16_t Reserved1; /* 0x04 */
326 u_int8_t Reserved2; /* 0x06 */
327 u_int8_t MsgFlags; /* 0x07 */
328 u_int8_t VP_ID; /* 0x08 */
329 u_int8_t VF_ID; /* 0x09 */
330 u_int16_t Reserved3; /* 0x0A */
331 u_int32_t SenseBufferLowAddress; /* 0x0C */
332 u_int16_t SGLFlags; /* 0x10 */
333 u_int8_t SenseBufferLength; /* 0x12 */
334 u_int8_t Reserved4; /* 0x13 */
335 u_int8_t SGLOffset0; /* 0x14 */
336 u_int8_t SGLOffset1; /* 0x15 */
337 u_int8_t SGLOffset2; /* 0x16 */
338 u_int8_t SGLOffset3; /* 0x17 */
339 u_int32_t SkipCount; /* 0x18 */
340 u_int32_t DataLength; /* 0x1C */
341 u_int32_t BidirectionalDataLength; /* 0x20 */
342 u_int16_t IoFlags; /* 0x24 */
343 u_int16_t EEDPFlags; /* 0x26 */
344 u_int32_t EEDPBlockSize; /* 0x28 */
345 u_int32_t SecondaryReferenceTag; /* 0x2C */
346 u_int16_t SecondaryApplicationTag; /* 0x30 */
347 u_int16_t ApplicationTagTranslationMask; /* 0x32 */
348 u_int8_t LUN[8]; /* 0x34 */
349 u_int32_t Control; /* 0x3C */
350 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
351 RAID_CONTEXT RaidContext; /* 0x60 */
352 MPI2_SGE_IO_UNION SGL; /* 0x80 */
353 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
354 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
355
356 /*
357 * MPT RAID MFA IO Descriptor.
358 */
359 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
360 u_int32_t RequestFlags : 8;
361 u_int32_t MessageAddress1 : 24; /* bits 31:8*/
362 u_int32_t MessageAddress2; /* bits 61:32 */
363 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
364
365 /* Default Request Descriptor */
366 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
367 {
368 u_int8_t RequestFlags; /* 0x00 */
369 u_int8_t MSIxIndex; /* 0x01 */
370 u_int16_t SMID; /* 0x02 */
371 u_int16_t LMID; /* 0x04 */
372 u_int16_t DescriptorTypeDependent; /* 0x06 */
373 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
374 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
375 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
376
377 /* High Priority Request Descriptor */
378 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
379 {
380 u_int8_t RequestFlags; /* 0x00 */
381 u_int8_t MSIxIndex; /* 0x01 */
382 u_int16_t SMID; /* 0x02 */
383 u_int16_t LMID; /* 0x04 */
384 u_int16_t Reserved1; /* 0x06 */
385 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
386 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
387 Mpi2HighPriorityRequestDescriptor_t,
388 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
389
390 /* SCSI IO Request Descriptor */
391 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
392 {
393 u_int8_t RequestFlags; /* 0x00 */
394 u_int8_t MSIxIndex; /* 0x01 */
395 u_int16_t SMID; /* 0x02 */
396 u_int16_t LMID; /* 0x04 */
397 u_int16_t DevHandle; /* 0x06 */
398 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
399 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
400 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
401
402 /* SCSI Target Request Descriptor */
403 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
404 {
405 u_int8_t RequestFlags; /* 0x00 */
406 u_int8_t MSIxIndex; /* 0x01 */
407 u_int16_t SMID; /* 0x02 */
408 u_int16_t LMID; /* 0x04 */
409 u_int16_t IoIndex; /* 0x06 */
410 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
411 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
412 Mpi2SCSITargetRequestDescriptor_t,
413 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
414
415 /* RAID Accelerator Request Descriptor */
416 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
417 {
418 u_int8_t RequestFlags; /* 0x00 */
419 u_int8_t MSIxIndex; /* 0x01 */
420 u_int16_t SMID; /* 0x02 */
421 u_int16_t LMID; /* 0x04 */
422 u_int16_t Reserved; /* 0x06 */
423 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
424 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
425 Mpi2RAIDAcceleratorRequestDescriptor_t,
426 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
427
428 /* union of Request Descriptors */
429 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION
430 {
431 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
432 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
433 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
434 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
435 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
436 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
437 union {
438 struct {
439 u_int32_t low;
440 u_int32_t high;
441 } u;
442 u_int64_t Words;
443 } addr;
444 } MRSAS_REQUEST_DESCRIPTOR_UNION;
445
446 /* Default Reply Descriptor */
447 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
448 {
449 u_int8_t ReplyFlags; /* 0x00 */
450 u_int8_t MSIxIndex; /* 0x01 */
451 u_int16_t DescriptorTypeDependent1; /* 0x02 */
452 u_int32_t DescriptorTypeDependent2; /* 0x04 */
453 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
454 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
455
456 /* Address Reply Descriptor */
457 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
458 {
459 u_int8_t ReplyFlags; /* 0x00 */
460 u_int8_t MSIxIndex; /* 0x01 */
461 u_int16_t SMID; /* 0x02 */
462 u_int32_t ReplyFrameAddress; /* 0x04 */
463 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
464 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
465
466 /* SCSI IO Success Reply Descriptor */
467 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
468 {
469 u_int8_t ReplyFlags; /* 0x00 */
470 u_int8_t MSIxIndex; /* 0x01 */
471 u_int16_t SMID; /* 0x02 */
472 u_int16_t TaskTag; /* 0x04 */
473 u_int16_t Reserved1; /* 0x06 */
474 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
475 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
476 Mpi2SCSIIOSuccessReplyDescriptor_t,
477 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
478
479 /* TargetAssist Success Reply Descriptor */
480 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
481 {
482 u_int8_t ReplyFlags; /* 0x00 */
483 u_int8_t MSIxIndex; /* 0x01 */
484 u_int16_t SMID; /* 0x02 */
485 u_int8_t SequenceNumber; /* 0x04 */
486 u_int8_t Reserved1; /* 0x05 */
487 u_int16_t IoIndex; /* 0x06 */
488 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
489 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
490 Mpi2TargetAssistSuccessReplyDescriptor_t,
491 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
492
493 /* Target Command Buffer Reply Descriptor */
494 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
495 {
496 u_int8_t ReplyFlags; /* 0x00 */
497 u_int8_t MSIxIndex; /* 0x01 */
498 u_int8_t VP_ID; /* 0x02 */
499 u_int8_t Flags; /* 0x03 */
500 u_int16_t InitiatorDevHandle; /* 0x04 */
501 u_int16_t IoIndex; /* 0x06 */
502 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
503 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
504 Mpi2TargetCommandBufferReplyDescriptor_t,
505 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
506
507 /* RAID Accelerator Success Reply Descriptor */
508 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
509 {
510 u_int8_t ReplyFlags; /* 0x00 */
511 u_int8_t MSIxIndex; /* 0x01 */
512 u_int16_t SMID; /* 0x02 */
513 u_int32_t Reserved; /* 0x04 */
514 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
515 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
516 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
517 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
518
519 /* union of Reply Descriptors */
520 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
521 {
522 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
523 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
524 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
525 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
526 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
527 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
528 u_int64_t Words;
529 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
530 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
531
532 typedef union {
533 volatile unsigned int val;
534 unsigned int val_rdonly;
535 } atomic_t;
536
537 #define atomic_read(v) atomic_load_acq_int(&(v)->val)
538 #define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
539 #define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1)
540 #define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1)
541
542 /* IOCInit Request message */
543 typedef struct _MPI2_IOC_INIT_REQUEST
544 {
545 u_int8_t WhoInit; /* 0x00 */
546 u_int8_t Reserved1; /* 0x01 */
547 u_int8_t ChainOffset; /* 0x02 */
548 u_int8_t Function; /* 0x03 */
549 u_int16_t Reserved2; /* 0x04 */
550 u_int8_t Reserved3; /* 0x06 */
551 u_int8_t MsgFlags; /* 0x07 */
552 u_int8_t VP_ID; /* 0x08 */
553 u_int8_t VF_ID; /* 0x09 */
554 u_int16_t Reserved4; /* 0x0A */
555 u_int16_t MsgVersion; /* 0x0C */
556 u_int16_t HeaderVersion; /* 0x0E */
557 u_int32_t Reserved5; /* 0x10 */
558 u_int16_t Reserved6; /* 0x14 */
559 u_int8_t Reserved7; /* 0x16 */
560 u_int8_t HostMSIxVectors; /* 0x17 */
561 u_int16_t Reserved8; /* 0x18 */
562 u_int16_t SystemRequestFrameSize; /* 0x1A */
563 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
564 u_int16_t ReplyFreeQueueDepth; /* 0x1E */
565 u_int32_t SenseBufferAddressHigh; /* 0x20 */
566 u_int32_t SystemReplyAddressHigh; /* 0x24 */
567 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */
568 u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */
569 u_int64_t ReplyFreeQueueAddress; /* 0x38 */
570 u_int64_t TimeStamp; /* 0x40 */
571 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
572 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
573
574 /*
575 * MR private defines
576 */
577 #define MR_PD_INVALID 0xFFFF
578 #define MAX_SPAN_DEPTH 8
579 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
580 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
581 #define MAX_ROW_SIZE 32
582 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
583 #define MAX_LOGICAL_DRIVES 64
584 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
585 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
586 #define MAX_ARRAYS 128
587 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
588 #define MAX_PHYSICAL_DEVICES 256
589 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
590 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD
591
592
593 /*******************************************************************
594 * RAID map related structures
595 ********************************************************************/
596
597 typedef struct _MR_DEV_HANDLE_INFO {
598 u_int16_t curDevHdl; // the device handle currently used by fw to issue the command.
599 u_int8_t validHandles; // bitmap of valid device handles.
600 u_int8_t reserved;
601 u_int16_t devHandle[2]; // 0x04 dev handles for all the paths.
602 } MR_DEV_HANDLE_INFO;
603
604 typedef struct _MR_ARRAY_INFO {
605 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
606 } MR_ARRAY_INFO; // 0x40, Total Size
607
608 typedef struct _MR_QUAD_ELEMENT {
609 u_int64_t logStart; // 0x00
610 u_int64_t logEnd; // 0x08
611 u_int64_t offsetInSpan; // 0x10
612 u_int32_t diff; // 0x18
613 u_int32_t reserved1; // 0x1C
614 } MR_QUAD_ELEMENT; // 0x20, Total size
615
616 typedef struct _MR_SPAN_INFO {
617 u_int32_t noElements; // 0x00
618 u_int32_t reserved1; // 0x04
619 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08
620 } MR_SPAN_INFO; // 0x108, Total size
621
622 typedef struct _MR_LD_SPAN_ { // SPAN structure
623 u_int64_t startBlk; // 0x00, starting block number in array
624 u_int64_t numBlks; // 0x08, number of blocks
625 u_int16_t arrayRef; // 0x10, array reference
626 u_int8_t spanRowSize; // 0x11, span row size
627 u_int8_t spanRowDataSize; // 0x12, span row data size
628 u_int8_t reserved[4]; // 0x13, reserved
629 } MR_LD_SPAN; // 0x18, Total Size
630
631 typedef struct _MR_SPAN_BLOCK_INFO {
632 u_int64_t num_rows; // number of rows/span
633 MR_LD_SPAN span; // 0x08
634 MR_SPAN_INFO block_span_info; // 0x20
635 } MR_SPAN_BLOCK_INFO;
636
637 typedef struct _MR_LD_RAID {
638 struct {
639 u_int32_t fpCapable :1;
640 u_int32_t reserved5 :3;
641 u_int32_t ldPiMode :4;
642 u_int32_t pdPiMode :4; // Every Pd has to be same.
643 u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE)
644 u_int32_t fpWriteCapable :1;
645 u_int32_t fpReadCapable :1;
646 u_int32_t fpWriteAcrossStripe :1;
647 u_int32_t fpReadAcrossStripe :1;
648 u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO
649 u_int32_t reserved4 :7;
650 } capability; // 0x00
651 u_int32_t reserved6;
652 u_int64_t size; // 0x08, LD size in blocks
653
654 u_int8_t spanDepth; // 0x10, Total Number of Spans
655 u_int8_t level; // 0x11, RAID level
656 u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.)
657 u_int8_t rowSize; // 0x13, number of disks in a row
658
659 u_int8_t rowDataSize; // 0x14, number of data disks in a row
660 u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK
661 u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E
662 u_int8_t SRL; // 0x17
663
664 u_int16_t targetId; // 0x18, ld Target Id.
665 u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE
666 u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc..
667 u_int8_t modFactor; // 0x1c, same as rowSize,
668 u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1
669 u_int16_t seqNum; // 0x1e, LD sequence number
670
671 struct {
672 u_int32_t ldSyncRequired:1; // This LD requires sync command before completing
673 u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead
674 u_int32_t reserved:30;
675 } flags; // 0x20
676
677 u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI
678 u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs
679 u_int8_t reserved2[3]; // 0x2D
680 u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD
681 struct {
682 u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16
683 u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK
684 u_int32_t reserved1:24; // 0x34
685 } exponent;
686 u_int8_t reserved3[0x80-0x38]; // 0x38
687 } MR_LD_RAID; // 0x80, Total Size
688
689 typedef struct _MR_LD_SPAN_MAP {
690 MR_LD_RAID ldRaid; // 0x00
691 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only.
692 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0
693 } MR_LD_SPAN_MAP; // 0x9E0
694
695 typedef struct _MR_FW_RAID_MAP {
696 u_int32_t totalSize; // total size of this structure, including this field.
697 union {
698 struct { // Simple method of version checking variables
699 u_int32_t maxLd;
700 u_int32_t maxSpanDepth;
701 u_int32_t maxRowSize;
702 u_int32_t maxPdCount;
703 u_int32_t maxArrays;
704 } validationInfo;
705 u_int32_t version[5];
706 u_int32_t reserved1[5];
707 } raid_desc;
708 u_int32_t ldCount; // count of lds.
709 u_int32_t Reserved1;
710 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20
711 // This doesn't correspond to
712 // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4
713 // and FW LD is 2, and there is only one LD, FW will populate the
714 // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to
715 // help reduce the entire strcture size if there are few LDs or
716 // driver is looking info for 1 LD only.
717 u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs
718 u_int8_t reserved2[7];
719 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8
720 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8
721 MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1];
722 } MR_FW_RAID_MAP; // 0x3288, Total Size
723
724 typedef struct _LD_LOAD_BALANCE_INFO
725 {
726 u_int8_t loadBalanceFlag;
727 u_int8_t reserved1;
728 u_int16_t raid1DevHandle[2];
729 atomic_t scsi_pending_cmds[2];
730 u_int64_t last_accessed_block[2];
731 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
732
733 /* SPAN_SET is info caclulated from span info from Raid map per ld */
734 typedef struct _LD_SPAN_SET {
735 u_int64_t log_start_lba;
736 u_int64_t log_end_lba;
737 u_int64_t span_row_start;
738 u_int64_t span_row_end;
739 u_int64_t data_strip_start;
740 u_int64_t data_strip_end;
741 u_int64_t data_row_start;
742 u_int64_t data_row_end;
743 u_int8_t strip_offset[MAX_SPAN_DEPTH];
744 u_int32_t span_row_data_width;
745 u_int32_t diff;
746 u_int32_t reserved[2];
747 }LD_SPAN_SET, *PLD_SPAN_SET;
748
749 typedef struct LOG_BLOCK_SPAN_INFO {
750 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
751 }LD_SPAN_INFO, *PLD_SPAN_INFO;
752
753 #pragma pack(1)
754 typedef struct _MR_FW_RAID_MAP_ALL {
755 MR_FW_RAID_MAP raidMap;
756 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
757 } MR_FW_RAID_MAP_ALL;
758 #pragma pack()
759
760 struct IO_REQUEST_INFO {
761 u_int64_t ldStartBlock;
762 u_int32_t numBlocks;
763 u_int16_t ldTgtId;
764 u_int8_t isRead;
765 u_int16_t devHandle;
766 u_int64_t pdBlock;
767 u_int8_t fpOkForIo;
768 u_int8_t IoforUnevenSpan;
769 u_int8_t start_span;
770 u_int8_t reserved;
771 u_int64_t start_row;
772 };
773
774 typedef struct _MR_LD_TARGET_SYNC {
775 u_int8_t targetId;
776 u_int8_t reserved;
777 u_int16_t seqNum;
778 } MR_LD_TARGET_SYNC;
779
780 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
781 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
782 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
783 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
784 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
785 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
786 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
787
788 union desc_value {
789 u_int64_t word;
790 struct {
791 u_int32_t low;
792 u_int32_t high;
793 } u;
794 };
795
796 /*******************************************************************
797 * Temporary command
798 ********************************************************************/
799 struct mrsas_tmp_dcmd {
800 bus_dma_tag_t tmp_dcmd_tag; // tag for tmp DMCD cmd
801 bus_dmamap_t tmp_dcmd_dmamap; // dmamap for tmp DCMD cmd
802 void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd
803 bus_addr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD
804 };
805
806 /*******************************************************************
807 * Register set, included legacy controllers 1068 and 1078,
808 * structure extended for 1078 registers
809 ********************************************************************/
810 #pragma pack(1)
811 typedef struct _mrsas_register_set {
812 u_int32_t doorbell; /*0000h*/
813 u_int32_t fusion_seq_offset; /*0004h*/
814 u_int32_t fusion_host_diag; /*0008h*/
815 u_int32_t reserved_01; /*000Ch*/
816
817 u_int32_t inbound_msg_0; /*0010h*/
818 u_int32_t inbound_msg_1; /*0014h*/
819 u_int32_t outbound_msg_0; /*0018h*/
820 u_int32_t outbound_msg_1; /*001Ch*/
821
822 u_int32_t inbound_doorbell; /*0020h*/
823 u_int32_t inbound_intr_status; /*0024h*/
824 u_int32_t inbound_intr_mask; /*0028h*/
825
826 u_int32_t outbound_doorbell; /*002Ch*/
827 u_int32_t outbound_intr_status; /*0030h*/
828 u_int32_t outbound_intr_mask; /*0034h*/
829
830 u_int32_t reserved_1[2]; /*0038h*/
831
832 u_int32_t inbound_queue_port; /*0040h*/
833 u_int32_t outbound_queue_port; /*0044h*/
834
835 u_int32_t reserved_2[9]; /*0048h*/
836 u_int32_t reply_post_host_index; /*006Ch*/
837 u_int32_t reserved_2_2[12]; /*0070h*/
838
839 u_int32_t outbound_doorbell_clear; /*00A0h*/
840
841 u_int32_t reserved_3[3]; /*00A4h*/
842
843 u_int32_t outbound_scratch_pad ; /*00B0h*/
844 u_int32_t outbound_scratch_pad_2; /*00B4h*/
845
846 u_int32_t reserved_4[2]; /*00B8h*/
847
848 u_int32_t inbound_low_queue_port ; /*00C0h*/
849
850 u_int32_t inbound_high_queue_port ; /*00C4h*/
851
852 u_int32_t reserved_5; /*00C8h*/
853 u_int32_t res_6[11]; /*CCh*/
854 u_int32_t host_diag;
855 u_int32_t seq_offset;
856 u_int32_t index_registers[807]; /*00CCh*/
857
858 } mrsas_reg_set;
859 #pragma pack()
860
861 /*******************************************************************
862 * Firmware Interface Defines
863 *******************************************************************
864 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
865 * for protocol between the software and firmware. Commands are
866 * issued using "message frames".
867 ******************************************************************/
868 /*
869 * FW posts its state in upper 4 bits of outbound_msg_0 register
870 */
871 #define MFI_STATE_MASK 0xF0000000
872 #define MFI_STATE_UNDEFINED 0x00000000
873 #define MFI_STATE_BB_INIT 0x10000000
874 #define MFI_STATE_FW_INIT 0x40000000
875 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
876 #define MFI_STATE_FW_INIT_2 0x70000000
877 #define MFI_STATE_DEVICE_SCAN 0x80000000
878 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
879 #define MFI_STATE_FLUSH_CACHE 0xA0000000
880 #define MFI_STATE_READY 0xB0000000
881 #define MFI_STATE_OPERATIONAL 0xC0000000
882 #define MFI_STATE_FAULT 0xF0000000
883 #define MFI_RESET_REQUIRED 0x00000001
884 #define MFI_RESET_ADAPTER 0x00000002
885 #define MEGAMFI_FRAME_SIZE 64
886 #define MRSAS_MFI_FRAME_SIZE 1024
887 #define MRSAS_MFI_SENSE_SIZE 128
888
889 /*
890 * During FW init, clear pending cmds & reset state using inbound_msg_0
891 *
892 * ABORT : Abort all pending cmds
893 * READY : Move from OPERATIONAL to READY state; discard queue info
894 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
895 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
896 * HOTPLUG : Resume from Hotplug
897 * MFI_STOP_ADP : Send signal to FW to stop processing
898 */
899
900 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20
901 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20
902 #define DIAG_WRITE_ENABLE (0x00000080)
903 #define DIAG_RESET_ADAPTER (0x00000004)
904
905 #define MFI_ADP_RESET 0x00000040
906 #define MFI_INIT_ABORT 0x00000001
907 #define MFI_INIT_READY 0x00000002
908 #define MFI_INIT_MFIMODE 0x00000004
909 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
910 #define MFI_INIT_HOTPLUG 0x00000010
911 #define MFI_STOP_ADP 0x00000020
912 #define MFI_RESET_FLAGS MFI_INIT_READY| \
913 MFI_INIT_MFIMODE| \
914 MFI_INIT_ABORT
915
916 /*
917 * MFI frame flags
918 */
919 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
920 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
921 #define MFI_FRAME_SGL32 0x0000
922 #define MFI_FRAME_SGL64 0x0002
923 #define MFI_FRAME_SENSE32 0x0000
924 #define MFI_FRAME_SENSE64 0x0004
925 #define MFI_FRAME_DIR_NONE 0x0000
926 #define MFI_FRAME_DIR_WRITE 0x0008
927 #define MFI_FRAME_DIR_READ 0x0010
928 #define MFI_FRAME_DIR_BOTH 0x0018
929 #define MFI_FRAME_IEEE 0x0020
930
931 /*
932 * Definition for cmd_status
933 */
934 #define MFI_CMD_STATUS_POLL_MODE 0xFF
935
936 /*
937 * MFI command opcodes
938 */
939 #define MFI_CMD_INIT 0x00
940 #define MFI_CMD_LD_READ 0x01
941 #define MFI_CMD_LD_WRITE 0x02
942 #define MFI_CMD_LD_SCSI_IO 0x03
943 #define MFI_CMD_PD_SCSI_IO 0x04
944 #define MFI_CMD_DCMD 0x05
945 #define MFI_CMD_ABORT 0x06
946 #define MFI_CMD_SMP 0x07
947 #define MFI_CMD_STP 0x08
948 #define MFI_CMD_INVALID 0xff
949
950 #define MR_DCMD_CTRL_GET_INFO 0x01010000
951 #define MR_DCMD_LD_GET_LIST 0x03010000
952 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
953 #define MR_FLUSH_CTRL_CACHE 0x01
954 #define MR_FLUSH_DISK_CACHE 0x02
955
956 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
957 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
958 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
959
960 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
961 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
962 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
963 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
964
965 #define MR_DCMD_CLUSTER 0x08000000
966 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
967 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
968 #define MR_DCMD_PD_LIST_QUERY 0x02010100
969
970 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200
971 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201
972 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202
973 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203
974 #define MAX_MR_ROW_SIZE 32
975 #define MR_CPX_DIR_WRITE 1
976 #define MR_CPX_DIR_READ 0
977 #define MR_CPX_VERSION 1
978
979 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics
980
981 #define MR_EVT_CFG_CLEARED 0x0004
982
983 #define MR_EVT_LD_STATE_CHANGE 0x0051
984 #define MR_EVT_PD_INSERTED 0x005b
985 #define MR_EVT_PD_REMOVED 0x0070
986 #define MR_EVT_LD_CREATED 0x008a
987 #define MR_EVT_LD_DELETED 0x008b
988 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
989 #define MR_EVT_LD_OFFLINE 0x00fc
990 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
991 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e
992
993 /*
994 * MFI command completion codes
995 */
996 enum MFI_STAT {
997 MFI_STAT_OK = 0x00,
998 MFI_STAT_INVALID_CMD = 0x01,
999 MFI_STAT_INVALID_DCMD = 0x02,
1000 MFI_STAT_INVALID_PARAMETER = 0x03,
1001 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1002 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1003 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1004 MFI_STAT_APP_IN_USE = 0x07,
1005 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1006 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1007 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1008 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1009 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1010 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1011 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1012 MFI_STAT_FLASH_BUSY = 0x0f,
1013 MFI_STAT_FLASH_ERROR = 0x10,
1014 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1015 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1016 MFI_STAT_FLASH_NOT_OPEN = 0x13,
1017 MFI_STAT_FLASH_NOT_STARTED = 0x14,
1018 MFI_STAT_FLUSH_FAILED = 0x15,
1019 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1020 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1021 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1022 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1023 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1024 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1025 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1026 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1027 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1028 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1029 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1030 MFI_STAT_MFC_HW_ERROR = 0x21,
1031 MFI_STAT_NO_HW_PRESENT = 0x22,
1032 MFI_STAT_NOT_FOUND = 0x23,
1033 MFI_STAT_NOT_IN_ENCL = 0x24,
1034 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1035 MFI_STAT_PD_TYPE_WRONG = 0x26,
1036 MFI_STAT_PR_DISABLED = 0x27,
1037 MFI_STAT_ROW_INDEX_INVALID = 0x28,
1038 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1039 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1040 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1041 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1042 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1043 MFI_STAT_SCSI_IO_FAILED = 0x2e,
1044 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1045 MFI_STAT_SHUTDOWN_FAILED = 0x30,
1046 MFI_STAT_TIME_NOT_SET = 0x31,
1047 MFI_STAT_WRONG_STATE = 0x32,
1048 MFI_STAT_LD_OFFLINE = 0x33,
1049 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1050 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1051 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1052 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1053 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1054 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1055
1056 MFI_STAT_INVALID_STATUS = 0xFF
1057 };
1058
1059 /*
1060 * Number of mailbox bytes in DCMD message frame
1061 */
1062 #define MFI_MBOX_SIZE 12
1063
1064 enum MR_EVT_CLASS {
1065
1066 MR_EVT_CLASS_DEBUG = -2,
1067 MR_EVT_CLASS_PROGRESS = -1,
1068 MR_EVT_CLASS_INFO = 0,
1069 MR_EVT_CLASS_WARNING = 1,
1070 MR_EVT_CLASS_CRITICAL = 2,
1071 MR_EVT_CLASS_FATAL = 3,
1072 MR_EVT_CLASS_DEAD = 4,
1073
1074 };
1075
1076 enum MR_EVT_LOCALE {
1077
1078 MR_EVT_LOCALE_LD = 0x0001,
1079 MR_EVT_LOCALE_PD = 0x0002,
1080 MR_EVT_LOCALE_ENCL = 0x0004,
1081 MR_EVT_LOCALE_BBU = 0x0008,
1082 MR_EVT_LOCALE_SAS = 0x0010,
1083 MR_EVT_LOCALE_CTRL = 0x0020,
1084 MR_EVT_LOCALE_CONFIG = 0x0040,
1085 MR_EVT_LOCALE_CLUSTER = 0x0080,
1086 MR_EVT_LOCALE_ALL = 0xffff,
1087
1088 };
1089
1090 enum MR_EVT_ARGS {
1091
1092 MR_EVT_ARGS_NONE,
1093 MR_EVT_ARGS_CDB_SENSE,
1094 MR_EVT_ARGS_LD,
1095 MR_EVT_ARGS_LD_COUNT,
1096 MR_EVT_ARGS_LD_LBA,
1097 MR_EVT_ARGS_LD_OWNER,
1098 MR_EVT_ARGS_LD_LBA_PD_LBA,
1099 MR_EVT_ARGS_LD_PROG,
1100 MR_EVT_ARGS_LD_STATE,
1101 MR_EVT_ARGS_LD_STRIP,
1102 MR_EVT_ARGS_PD,
1103 MR_EVT_ARGS_PD_ERR,
1104 MR_EVT_ARGS_PD_LBA,
1105 MR_EVT_ARGS_PD_LBA_LD,
1106 MR_EVT_ARGS_PD_PROG,
1107 MR_EVT_ARGS_PD_STATE,
1108 MR_EVT_ARGS_PCI,
1109 MR_EVT_ARGS_RATE,
1110 MR_EVT_ARGS_STR,
1111 MR_EVT_ARGS_TIME,
1112 MR_EVT_ARGS_ECC,
1113 MR_EVT_ARGS_LD_PROP,
1114 MR_EVT_ARGS_PD_SPARE,
1115 MR_EVT_ARGS_PD_INDEX,
1116 MR_EVT_ARGS_DIAG_PASS,
1117 MR_EVT_ARGS_DIAG_FAIL,
1118 MR_EVT_ARGS_PD_LBA_LBA,
1119 MR_EVT_ARGS_PORT_PHY,
1120 MR_EVT_ARGS_PD_MISSING,
1121 MR_EVT_ARGS_PD_ADDRESS,
1122 MR_EVT_ARGS_BITMAP,
1123 MR_EVT_ARGS_CONNECTOR,
1124 MR_EVT_ARGS_PD_PD,
1125 MR_EVT_ARGS_PD_FRU,
1126 MR_EVT_ARGS_PD_PATHINFO,
1127 MR_EVT_ARGS_PD_POWER_STATE,
1128 MR_EVT_ARGS_GENERIC,
1129 };
1130
1131
1132 /*
1133 * Thunderbolt (and later) Defines
1134 */
1135 #define MRSAS_MAX_SZ_CHAIN_FRAME 1024
1136 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
1137 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
1138 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
1139 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
1140 #define MRSAS_LOAD_BALANCE_FLAG 0x1
1141 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1
1142 #define HOST_DIAG_WRITE_ENABLE 0x80
1143 #define HOST_DIAG_RESET_ADAPTER 0x4
1144 #define MRSAS_TBOLT_MAX_RESET_TRIES 3
1145 #define MRSAS_MAX_MFI_CMDS 32
1146
1147 /*
1148 * Invader Defines
1149 */
1150 #define MPI2_TYPE_CUDA 0x2
1151 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
1152 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
1153 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
1154 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
1155 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
1156
1157 /*
1158 * T10 PI defines
1159 */
1160 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
1161 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
1162 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9
1163 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB
1164 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18
1165 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20
1166 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60
1167 #define MRSAS_SCSIBLOCKSIZE 512
1168
1169 /*
1170 * Raid context flags
1171 */
1172 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
1173 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
1174 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1175 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1176 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1177 } MR_RAID_FLAGS_IO_SUB_TYPE;
1178
1179 /*
1180 * Request descriptor types
1181 */
1182 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
1183 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1
1184 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
1185 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
1186 #define MRSAS_FP_CMD_LEN 16
1187 #define MRSAS_FUSION_IN_RESET 0
1188
1189 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
1190 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
1191 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
1192 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
1193
1194 /*
1195 * Define region lock types
1196 */
1197 typedef enum _REGION_TYPE {
1198 REGION_TYPE_UNUSED = 0, // lock is currently not active
1199 REGION_TYPE_SHARED_READ = 1, // shared lock (for reads)
1200 REGION_TYPE_SHARED_WRITE = 2,
1201 REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes)
1202 } REGION_TYPE;
1203
1204 /*
1205 * MR private defines
1206 */
1207 #define MR_PD_INVALID 0xFFFF
1208 #define MAX_SPAN_DEPTH 8
1209 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
1210 #define MAX_ROW_SIZE 32
1211 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
1212 #define MAX_LOGICAL_DRIVES 64
1213 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
1214 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
1215 #define MAX_ARRAYS 128
1216 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
1217 #define MAX_PHYSICAL_DEVICES 256
1218 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
1219 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
1220
1221 /*
1222 * SCSI-CAM Related Defines
1223 */
1224 #define MRSAS_SCSI_MAX_LUNS 0 //zero for now
1225 #define MRSAS_SCSI_INITIATOR_ID 255
1226 #define MRSAS_SCSI_MAX_CMDS 8
1227 #define MRSAS_SCSI_MAX_CDB_LEN 16
1228 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96
1229 #define MRSAS_MAX_SGL 70
1230 #define MRSAS_MAX_IO_SIZE (256 * 1024)
1231 #define MRSAS_INTERNAL_CMDS 32
1232
1233 /* Request types */
1234 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0
1235 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1
1236 #define MRSAS_REQ_TYPE_PASSTHRU 0x2
1237 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3
1238 #define MRSAS_REQ_TYPE_SCSI_IO 0x4
1239
1240 /* Request states */
1241 #define MRSAS_REQ_STATE_FREE 0
1242 #define MRSAS_REQ_STATE_BUSY 1
1243 #define MRSAS_REQ_STATE_TRAN 2
1244 #define MRSAS_REQ_STATE_COMPLETE 3
1245
1246 enum mrsas_req_flags {
1247 MRSAS_DIR_UNKNOWN = 0x1,
1248 MRSAS_DIR_IN = 0x2,
1249 MRSAS_DIR_OUT = 0x4,
1250 MRSAS_DIR_NONE = 0x8,
1251 };
1252
1253 /*
1254 * Adapter Reset States
1255 */
1256 enum {
1257 MRSAS_HBA_OPERATIONAL = 0,
1258 MRSAS_ADPRESET_SM_INFAULT = 1,
1259 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1260 MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1261 MRSAS_HW_CRITICAL_ERROR = 4,
1262 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1263 };
1264
1265 /*
1266 * MPT Command Structure
1267 */
1268 struct mrsas_mpt_cmd {
1269 MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1270 bus_addr_t io_request_phys_addr;
1271 MPI2_SGE_IO_UNION *chain_frame;
1272 bus_addr_t chain_frame_phys_addr;
1273 u_int32_t sge_count;
1274 u_int8_t *sense;
1275 bus_addr_t sense_phys_addr;
1276 u_int8_t retry_for_fw_reset;
1277 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1278 u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete
1279 u_int32_t index;
1280 u_int8_t flags;
1281 u_int8_t load_balance;
1282 bus_size_t length; // request length
1283 u_int32_t error_code; // error during request dmamap load
1284 bus_dmamap_t data_dmamap;
1285 void *data;
1286 union ccb *ccb_ptr; // pointer to ccb
1287 struct callout cm_callout;
1288 struct mrsas_softc *sc;
1289 TAILQ_ENTRY(mrsas_mpt_cmd) next;
1290 };
1291
1292 /*
1293 * MFI Command Structure
1294 */
1295 struct mrsas_mfi_cmd {
1296 union mrsas_frame *frame;
1297 bus_dmamap_t frame_dmamap; // mfi frame dmamap
1298 void *frame_mem; // mfi frame virtual addr
1299 bus_addr_t frame_phys_addr; // mfi frame physical addr
1300 u_int8_t *sense;
1301 bus_dmamap_t sense_dmamap; // mfi sense dmamap
1302 void *sense_mem; // mfi sense virtual addr
1303 bus_addr_t sense_phys_addr;
1304 u_int32_t index;
1305 u_int8_t sync_cmd;
1306 u_int8_t cmd_status;
1307 u_int8_t abort_aen;
1308 u_int8_t retry_for_fw_reset;
1309 struct mrsas_softc *sc;
1310 union ccb *ccb_ptr;
1311 union {
1312 struct {
1313 u_int16_t smid;
1314 u_int16_t resvd;
1315 } context;
1316 u_int32_t frame_count;
1317 } cmd_id;
1318 TAILQ_ENTRY(mrsas_mfi_cmd) next;
1319 };
1320
1321
1322 /*
1323 * define constants for device list query options
1324 */
1325 enum MR_PD_QUERY_TYPE {
1326 MR_PD_QUERY_TYPE_ALL = 0,
1327 MR_PD_QUERY_TYPE_STATE = 1,
1328 MR_PD_QUERY_TYPE_POWER_STATE = 2,
1329 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1330 MR_PD_QUERY_TYPE_SPEED = 4,
1331 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1332 };
1333
1334 #define MR_EVT_CFG_CLEARED 0x0004
1335 #define MR_EVT_LD_STATE_CHANGE 0x0051
1336 #define MR_EVT_PD_INSERTED 0x005b
1337 #define MR_EVT_PD_REMOVED 0x0070
1338 #define MR_EVT_LD_CREATED 0x008a
1339 #define MR_EVT_LD_DELETED 0x008b
1340 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1341 #define MR_EVT_LD_OFFLINE 0x00fc
1342 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1343
1344 enum MR_PD_STATE {
1345 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1346 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1347 MR_PD_STATE_HOT_SPARE = 0x02,
1348 MR_PD_STATE_OFFLINE = 0x10,
1349 MR_PD_STATE_FAILED = 0x11,
1350 MR_PD_STATE_REBUILD = 0x14,
1351 MR_PD_STATE_ONLINE = 0x18,
1352 MR_PD_STATE_COPYBACK = 0x20,
1353 MR_PD_STATE_SYSTEM = 0x40,
1354 };
1355
1356 /*
1357 * defines the physical drive address structure
1358 */
1359 #pragma pack(1)
1360 struct MR_PD_ADDRESS {
1361 u_int16_t deviceId;
1362 u_int16_t enclDeviceId;
1363
1364 union {
1365 struct {
1366 u_int8_t enclIndex;
1367 u_int8_t slotNumber;
1368 } mrPdAddress;
1369 struct {
1370 u_int8_t enclPosition;
1371 u_int8_t enclConnectorIndex;
1372 } mrEnclAddress;
1373 } u1;
1374 u_int8_t scsiDevType;
1375 union {
1376 u_int8_t connectedPortBitmap;
1377 u_int8_t connectedPortNumbers;
1378 } u2;
1379 u_int64_t sasAddr[2];
1380 };
1381 #pragma pack()
1382
1383 /*
1384 * defines the physical drive list structure
1385 */
1386 #pragma pack(1)
1387 struct MR_PD_LIST {
1388 u_int32_t size;
1389 u_int32_t count;
1390 struct MR_PD_ADDRESS addr[1];
1391 };
1392 #pragma pack()
1393
1394 #pragma pack(1)
1395 struct mrsas_pd_list {
1396 u_int16_t tid;
1397 u_int8_t driveType;
1398 u_int8_t driveState;
1399 };
1400 #pragma pack()
1401
1402 /*
1403 * defines the logical drive reference structure
1404 */
1405 typedef union _MR_LD_REF { // LD reference structure
1406 struct {
1407 u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID)
1408 u_int8_t reserved; // reserved to make in line with MR_PD_REF
1409 u_int16_t seqNum; // Sequence Number
1410 } ld_context;
1411 u_int32_t ref; // shorthand reference to full 32-bits
1412 } MR_LD_REF; // 4 bytes
1413
1414
1415 /*
1416 * defines the logical drive list structure
1417 */
1418 #pragma pack(1)
1419 struct MR_LD_LIST {
1420 u_int32_t ldCount; // number of LDs
1421 u_int32_t reserved; // pad to 8-byte boundary
1422 struct {
1423 MR_LD_REF ref; // LD reference
1424 u_int8_t state; // current LD state (MR_LD_STATE)
1425 u_int8_t reserved[3]; // pad to 8-byte boundary
1426 u_int64_t size; // LD size
1427 } ldList[MAX_LOGICAL_DRIVES];
1428 };
1429 #pragma pack()
1430
1431 /*
1432 * SAS controller properties
1433 */
1434 #pragma pack(1)
1435 struct mrsas_ctrl_prop {
1436 u_int16_t seq_num;
1437 u_int16_t pred_fail_poll_interval;
1438 u_int16_t intr_throttle_count;
1439 u_int16_t intr_throttle_timeouts;
1440 u_int8_t rebuild_rate;
1441 u_int8_t patrol_read_rate;
1442 u_int8_t bgi_rate;
1443 u_int8_t cc_rate;
1444 u_int8_t recon_rate;
1445 u_int8_t cache_flush_interval;
1446 u_int8_t spinup_drv_count;
1447 u_int8_t spinup_delay;
1448 u_int8_t cluster_enable;
1449 u_int8_t coercion_mode;
1450 u_int8_t alarm_enable;
1451 u_int8_t disable_auto_rebuild;
1452 u_int8_t disable_battery_warn;
1453 u_int8_t ecc_bucket_size;
1454 u_int16_t ecc_bucket_leak_rate;
1455 u_int8_t restore_hotspare_on_insertion;
1456 u_int8_t expose_encl_devices;
1457 u_int8_t maintainPdFailHistory;
1458 u_int8_t disallowHostRequestReordering;
1459 u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency
1460 u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE)
1461 u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes
1462 // like SGPIO, i2c SEP using h/w mechansim
1463 // like GPIO pins.
1464 // 1 - disable auto detect SGPIO,
1465 // 2 - disable i2c SEP auto detect
1466 // 3 - disable both auto detect
1467 u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in
1468 // snapshot repository, for metadata and user data.
1469 // 1=5%, 2=10%, 3=15% and so on.
1470 /*
1471 * Add properties that can be controlled by a bit in the following structure.
1472 */
1473 struct {
1474 u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack
1475 // (0=copback enabled)
1476 u_int32_t SMARTerEnabled : 1;
1477 u_int32_t prCorrectUnconfiguredAreas : 1;
1478 u_int32_t useFdeOnly : 1;
1479 u_int32_t disableNCQ : 1;
1480 u_int32_t SSDSMARTerEnabled : 1;
1481 u_int32_t SSDPatrolReadEnabled : 1;
1482 u_int32_t enableSpinDownUnconfigured : 1;
1483 u_int32_t autoEnhancedImport : 1;
1484 u_int32_t enableSecretKeyControl : 1;
1485 u_int32_t disableOnlineCtrlReset : 1;
1486 u_int32_t allowBootWithPinnedCache : 1;
1487 u_int32_t disableSpinDownHS : 1;
1488 u_int32_t enableJBOD : 1;
1489 u_int32_t reserved :18;
1490 } OnOffProperties;
1491 u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto
1492 // snapshot in snapshot repository, for
1493 // metadata and user data.
1494 // 1=5%, 2=10%, 3=15% and so on.
1495 u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a %
1496 // of source LD capacity. 0=READ only.
1497 // 1=5%, 2=10%, 3=15% and so on
1498 u_int16_t spinDownTime; // # of idle minutes before device is spun
1499 // down (0=use FW defaults).
1500 u_int8_t reserved[24];
1501
1502 };
1503 #pragma pack()
1504
1505
1506 /*
1507 * SAS controller information
1508 */
1509 //#pragma pack(1)
1510 struct mrsas_ctrl_info {
1511 /*
1512 * PCI device information
1513 */
1514 struct {
1515 u_int16_t vendor_id;
1516 u_int16_t device_id;
1517 u_int16_t sub_vendor_id;
1518 u_int16_t sub_device_id;
1519 u_int8_t reserved[24];
1520 } __packed pci;
1521 /*
1522 * Host interface information
1523 */
1524 struct {
1525 u_int8_t PCIX:1;
1526 u_int8_t PCIE:1;
1527 u_int8_t iSCSI:1;
1528 u_int8_t SAS_3G:1;
1529 u_int8_t reserved_0:4;
1530 u_int8_t reserved_1[6];
1531 u_int8_t port_count;
1532 u_int64_t port_addr[8];
1533 } __packed host_interface;
1534 /*
1535 * Device (backend) interface information
1536 */
1537 struct {
1538 u_int8_t SPI:1;
1539 u_int8_t SAS_3G:1;
1540 u_int8_t SATA_1_5G:1;
1541 u_int8_t SATA_3G:1;
1542 u_int8_t reserved_0:4;
1543 u_int8_t reserved_1[6];
1544 u_int8_t port_count;
1545 u_int64_t port_addr[8];
1546 } __packed device_interface;
1547
1548 /*
1549 * List of components residing in flash. All str are null terminated
1550 */
1551 u_int32_t image_check_word;
1552 u_int32_t image_component_count;
1553
1554 struct {
1555 char name[8];
1556 char version[32];
1557 char build_date[16];
1558 char built_time[16];
1559 } __packed image_component[8];
1560 /*
1561 * List of flash components that have been flashed on the card, but
1562 * are not in use, pending reset of the adapter. This list will be
1563 * empty if a flash operation has not occurred. All stings are null
1564 * terminated
1565 */
1566 u_int32_t pending_image_component_count;
1567
1568 struct {
1569 char name[8];
1570 char version[32];
1571 char build_date[16];
1572 char build_time[16];
1573 } __packed pending_image_component[8];
1574
1575 u_int8_t max_arms;
1576 u_int8_t max_spans;
1577 u_int8_t max_arrays;
1578 u_int8_t max_lds;
1579 char product_name[80];
1580 char serial_no[32];
1581
1582 /*
1583 * Other physical/controller/operation information. Indicates the
1584 * presence of the hardware
1585 */
1586 struct {
1587 u_int32_t bbu:1;
1588 u_int32_t alarm:1;
1589 u_int32_t nvram:1;
1590 u_int32_t uart:1;
1591 u_int32_t reserved:28;
1592 } __packed hw_present;
1593
1594 u_int32_t current_fw_time;
1595
1596 /*
1597 * Maximum data transfer sizes
1598 */
1599 u_int16_t max_concurrent_cmds;
1600 u_int16_t max_sge_count;
1601 u_int32_t max_request_size;
1602
1603 /*
1604 * Logical and physical device counts
1605 */
1606 u_int16_t ld_present_count;
1607 u_int16_t ld_degraded_count;
1608 u_int16_t ld_offline_count;
1609
1610 u_int16_t pd_present_count;
1611 u_int16_t pd_disk_present_count;
1612 u_int16_t pd_disk_pred_failure_count;
1613 u_int16_t pd_disk_failed_count;
1614
1615 /*
1616 * Memory size information
1617 */
1618 u_int16_t nvram_size;
1619 u_int16_t memory_size;
1620 u_int16_t flash_size;
1621
1622 /*
1623 * Error counters
1624 */
1625 u_int16_t mem_correctable_error_count;
1626 u_int16_t mem_uncorrectable_error_count;
1627
1628 /*
1629 * Cluster information
1630 */
1631 u_int8_t cluster_permitted;
1632 u_int8_t cluster_active;
1633
1634 /*
1635 * Additional max data transfer sizes
1636 */
1637 u_int16_t max_strips_per_io;
1638
1639 /*
1640 * Controller capabilities structures
1641 */
1642 struct {
1643 u_int32_t raid_level_0:1;
1644 u_int32_t raid_level_1:1;
1645 u_int32_t raid_level_5:1;
1646 u_int32_t raid_level_1E:1;
1647 u_int32_t raid_level_6:1;
1648 u_int32_t reserved:27;
1649 } __packed raid_levels;
1650
1651 struct {
1652 u_int32_t rbld_rate:1;
1653 u_int32_t cc_rate:1;
1654 u_int32_t bgi_rate:1;
1655 u_int32_t recon_rate:1;
1656 u_int32_t patrol_rate:1;
1657 u_int32_t alarm_control:1;
1658 u_int32_t cluster_supported:1;
1659 u_int32_t bbu:1;
1660 u_int32_t spanning_allowed:1;
1661 u_int32_t dedicated_hotspares:1;
1662 u_int32_t revertible_hotspares:1;
1663 u_int32_t foreign_config_import:1;
1664 u_int32_t self_diagnostic:1;
1665 u_int32_t mixed_redundancy_arr:1;
1666 u_int32_t global_hot_spares:1;
1667 u_int32_t reserved:17;
1668 } __packed adapter_operations;
1669
1670 struct {
1671 u_int32_t read_policy:1;
1672 u_int32_t write_policy:1;
1673 u_int32_t io_policy:1;
1674 u_int32_t access_policy:1;
1675 u_int32_t disk_cache_policy:1;
1676 u_int32_t reserved:27;
1677 } __packed ld_operations;
1678
1679 struct {
1680 u_int8_t min;
1681 u_int8_t max;
1682 u_int8_t reserved[2];
1683 } __packed stripe_sz_ops;
1684
1685 struct {
1686 u_int32_t force_online:1;
1687 u_int32_t force_offline:1;
1688 u_int32_t force_rebuild:1;
1689 u_int32_t reserved:29;
1690 } __packed pd_operations;
1691
1692 struct {
1693 u_int32_t ctrl_supports_sas:1;
1694 u_int32_t ctrl_supports_sata:1;
1695 u_int32_t allow_mix_in_encl:1;
1696 u_int32_t allow_mix_in_ld:1;
1697 u_int32_t allow_sata_in_cluster:1;
1698 u_int32_t reserved:27;
1699 } __packed pd_mix_support;
1700
1701 /*
1702 * Define ECC single-bit-error bucket information
1703 */
1704 u_int8_t ecc_bucket_count;
1705 u_int8_t reserved_2[11];
1706
1707 /*
1708 * Include the controller properties (changeable items)
1709 */
1710 struct mrsas_ctrl_prop properties;
1711
1712 /*
1713 * Define FW pkg version (set in envt v'bles on OEM basis)
1714 */
1715 char package_version[0x60];
1716
1717 /*
1718 * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8,
1719 * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be
1720 * populated in deviceInterfacePortAddr2.
1721 */
1722 u_int64_t deviceInterfacePortAddr2[8]; //0x6a0
1723 u_int8_t reserved3[128]; //0x6e0
1724
1725 struct { //0x760
1726 u_int16_t minPdRaidLevel_0 : 4;
1727 u_int16_t maxPdRaidLevel_0 : 12;
1728
1729 u_int16_t minPdRaidLevel_1 : 4;
1730 u_int16_t maxPdRaidLevel_1 : 12;
1731
1732 u_int16_t minPdRaidLevel_5 : 4;
1733 u_int16_t maxPdRaidLevel_5 : 12;
1734
1735 u_int16_t minPdRaidLevel_1E : 4;
1736 u_int16_t maxPdRaidLevel_1E : 12;
1737
1738 u_int16_t minPdRaidLevel_6 : 4;
1739 u_int16_t maxPdRaidLevel_6 : 12;
1740
1741 u_int16_t minPdRaidLevel_10 : 4;
1742 u_int16_t maxPdRaidLevel_10 : 12;
1743
1744 u_int16_t minPdRaidLevel_50 : 4;
1745 u_int16_t maxPdRaidLevel_50 : 12;
1746
1747 u_int16_t minPdRaidLevel_60 : 4;
1748 u_int16_t maxPdRaidLevel_60 : 12;
1749
1750 u_int16_t minPdRaidLevel_1E_RLQ0 : 4;
1751 u_int16_t maxPdRaidLevel_1E_RLQ0 : 12;
1752
1753 u_int16_t minPdRaidLevel_1E0_RLQ0 : 4;
1754 u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12;
1755
1756 u_int16_t reserved[6];
1757 } pdsForRaidLevels;
1758
1759 u_int16_t maxPds; //0x780
1760 u_int16_t maxDedHSPs; //0x782
1761 u_int16_t maxGlobalHSPs; //0x784
1762 u_int16_t ddfSize; //0x786
1763 u_int8_t maxLdsPerArray; //0x788
1764 u_int8_t partitionsInDDF; //0x789
1765 u_int8_t lockKeyBinding; //0x78a
1766 u_int8_t maxPITsPerLd; //0x78b
1767 u_int8_t maxViewsPerLd; //0x78c
1768 u_int8_t maxTargetId; //0x78d
1769 u_int16_t maxBvlVdSize; //0x78e
1770
1771 u_int16_t maxConfigurableSSCSize; //0x790
1772 u_int16_t currentSSCsize; //0x792
1773
1774 char expanderFwVersion[12]; //0x794
1775
1776 u_int16_t PFKTrialTimeRemaining; //0x7A0
1777
1778 u_int16_t cacheMemorySize; //0x7A2
1779
1780 struct { //0x7A4
1781 u_int32_t supportPIcontroller :1;
1782 u_int32_t supportLdPIType1 :1;
1783 u_int32_t supportLdPIType2 :1;
1784 u_int32_t supportLdPIType3 :1;
1785 u_int32_t supportLdBBMInfo :1;
1786 u_int32_t supportShieldState :1;
1787 u_int32_t blockSSDWriteCacheChange :1;
1788 u_int32_t supportSuspendResumeBGops :1;
1789 u_int32_t supportEmergencySpares :1;
1790 u_int32_t supportSetLinkSpeed :1;
1791 u_int32_t supportBootTimePFKChange :1;
1792 u_int32_t supportJBOD :1;
1793 u_int32_t disableOnlinePFKChange :1;
1794 u_int32_t supportPerfTuning :1;
1795 u_int32_t supportSSDPatrolRead :1;
1796 u_int32_t realTimeScheduler :1;
1797
1798 u_int32_t supportResetNow :1;
1799 u_int32_t supportEmulatedDrives :1;
1800 u_int32_t headlessMode :1;
1801 u_int32_t dedicatedHotSparesLimited :1;
1802
1803
1804 u_int32_t supportUnevenSpans :1;
1805 u_int32_t reserved :11;
1806 } adapterOperations2;
1807
1808 u_int8_t driverVersion[32]; //0x7A8
1809 u_int8_t maxDAPdCountSpinup60; //0x7C8
1810 u_int8_t temperatureROC; //0x7C9
1811 u_int8_t temperatureCtrl; //0x7CA
1812 u_int8_t reserved4; //0x7CB
1813 u_int16_t maxConfigurablePds; //0x7CC
1814
1815
1816 u_int8_t reserved5[2]; //0x7CD reserved for future use
1817
1818 /*
1819 * HA cluster information
1820 */
1821 struct {
1822 u_int32_t peerIsPresent :1;
1823 u_int32_t peerIsIncompatible :1;
1824
1825 u_int32_t hwIncompatible :1;
1826 u_int32_t fwVersionMismatch :1;
1827 u_int32_t ctrlPropIncompatible :1;
1828 u_int32_t premiumFeatureMismatch :1;
1829 u_int32_t reserved :26;
1830 } cluster;
1831
1832 char clusterId[16]; //0x7D4
1833
1834 u_int8_t pad[0x800-0x7E4]; //0x7E4
1835 } __packed;
1836
1837 /*
1838 * Ld and PD Max Support Defines
1839 */
1840 #define MRSAS_MAX_PD 256
1841 #define MRSAS_MAX_LD 64
1842
1843 /*
1844 * When SCSI mid-layer calls driver's reset routine, driver waits for
1845 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1846 * that the driver cannot _actually_ abort or reset pending commands. While
1847 * it is waiting for the commands to complete, it prints a diagnostic message
1848 * every MRSAS_RESET_NOTICE_INTERVAL seconds
1849 */
1850 #define MRSAS_RESET_WAIT_TIME 180
1851 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180
1852 #define MRSAS_IOC_INIT_WAIT_TIME 60
1853 #define MRSAS_RESET_NOTICE_INTERVAL 5
1854 #define MRSAS_IOCTL_CMD 0
1855 #define MRSAS_DEFAULT_CMD_TIMEOUT 90
1856 #define MRSAS_THROTTLE_QUEUE_DEPTH 16
1857
1858 /*
1859 * FW reports the maximum of number of commands that it can accept (maximum
1860 * commands that can be outstanding) at any time. The driver must report a
1861 * lower number to the mid layer because it can issue a few internal commands
1862 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1863 * is shown below
1864 */
1865 #define MRSAS_INT_CMDS 32
1866 #define MRSAS_SKINNY_INT_CMDS 5
1867 #define MRSAS_MAX_MSIX_QUEUES 16
1868
1869 /*
1870 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1871 * SGLs based on the size of bus_addr_t
1872 */
1873 #define IS_DMA64 (sizeof(bus_addr_t) == 8)
1874
1875 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt
1876 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1877 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1878 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt
1879
1880 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1881 #define MFI_POLL_TIMEOUT_SECS 60
1882
1883 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1884 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1885 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001
1886 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1887 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1888 #define MFI_1068_PCSR_OFFSET 0x84
1889 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1890 #define MFI_1068_FW_READY 0xDDDD0000
1891
1892 #pragma pack(1)
1893 struct mrsas_sge32 {
1894 u_int32_t phys_addr;
1895 u_int32_t length;
1896 };
1897 #pragma pack()
1898
1899 #pragma pack(1)
1900 struct mrsas_sge64 {
1901 u_int64_t phys_addr;
1902 u_int32_t length;
1903 };
1904 #pragma pack()
1905
1906 #pragma pack()
1907 union mrsas_sgl {
1908 struct mrsas_sge32 sge32[1];
1909 struct mrsas_sge64 sge64[1];
1910 };
1911 #pragma pack()
1912
1913 #pragma pack(1)
1914 struct mrsas_header {
1915 u_int8_t cmd; /*00e */
1916 u_int8_t sense_len; /*01h */
1917 u_int8_t cmd_status; /*02h */
1918 u_int8_t scsi_status; /*03h */
1919
1920 u_int8_t target_id; /*04h */
1921 u_int8_t lun; /*05h */
1922 u_int8_t cdb_len; /*06h */
1923 u_int8_t sge_count; /*07h */
1924
1925 u_int32_t context; /*08h */
1926 u_int32_t pad_0; /*0Ch */
1927
1928 u_int16_t flags; /*10h */
1929 u_int16_t timeout; /*12h */
1930 u_int32_t data_xferlen; /*14h */
1931 };
1932 #pragma pack()
1933
1934 #pragma pack(1)
1935 struct mrsas_init_frame {
1936 u_int8_t cmd; /*00h */
1937 u_int8_t reserved_0; /*01h */
1938 u_int8_t cmd_status; /*02h */
1939
1940 u_int8_t reserved_1; /*03h */
1941 u_int32_t reserved_2; /*04h */
1942
1943 u_int32_t context; /*08h */
1944 u_int32_t pad_0; /*0Ch */
1945
1946 u_int16_t flags; /*10h */
1947 u_int16_t reserved_3; /*12h */
1948 u_int32_t data_xfer_len; /*14h */
1949
1950 u_int32_t queue_info_new_phys_addr_lo; /*18h */
1951 u_int32_t queue_info_new_phys_addr_hi; /*1Ch */
1952 u_int32_t queue_info_old_phys_addr_lo; /*20h */
1953 u_int32_t queue_info_old_phys_addr_hi; /*24h */
1954 u_int32_t driver_ver_lo; /*28h */
1955 u_int32_t driver_ver_hi; /*2Ch */
1956 u_int32_t reserved_4[4]; /*30h */
1957 };
1958 #pragma pack()
1959
1960 #pragma pack(1)
1961 struct mrsas_io_frame {
1962 u_int8_t cmd; /*00h */
1963 u_int8_t sense_len; /*01h */
1964 u_int8_t cmd_status; /*02h */
1965 u_int8_t scsi_status; /*03h */
1966
1967 u_int8_t target_id; /*04h */
1968 u_int8_t access_byte; /*05h */
1969 u_int8_t reserved_0; /*06h */
1970 u_int8_t sge_count; /*07h */
1971
1972 u_int32_t context; /*08h */
1973 u_int32_t pad_0; /*0Ch */
1974
1975 u_int16_t flags; /*10h */
1976 u_int16_t timeout; /*12h */
1977 u_int32_t lba_count; /*14h */
1978
1979 u_int32_t sense_buf_phys_addr_lo; /*18h */
1980 u_int32_t sense_buf_phys_addr_hi; /*1Ch */
1981
1982 u_int32_t start_lba_lo; /*20h */
1983 u_int32_t start_lba_hi; /*24h */
1984
1985 union mrsas_sgl sgl; /*28h */
1986 };
1987 #pragma pack()
1988
1989 #pragma pack(1)
1990 struct mrsas_pthru_frame {
1991 u_int8_t cmd; /*00h */
1992 u_int8_t sense_len; /*01h */
1993 u_int8_t cmd_status; /*02h */
1994 u_int8_t scsi_status; /*03h */
1995
1996 u_int8_t target_id; /*04h */
1997 u_int8_t lun; /*05h */
1998 u_int8_t cdb_len; /*06h */
1999 u_int8_t sge_count; /*07h */
2000
2001 u_int32_t context; /*08h */
2002 u_int32_t pad_0; /*0Ch */
2003
2004 u_int16_t flags; /*10h */
2005 u_int16_t timeout; /*12h */
2006 u_int32_t data_xfer_len; /*14h */
2007
2008 u_int32_t sense_buf_phys_addr_lo; /*18h */
2009 u_int32_t sense_buf_phys_addr_hi; /*1Ch */
2010
2011 u_int8_t cdb[16]; /*20h */
2012 union mrsas_sgl sgl; /*30h */
2013 };
2014 #pragma pack()
2015
2016 #pragma pack(1)
2017 struct mrsas_dcmd_frame {
2018 u_int8_t cmd; /*00h */
2019 u_int8_t reserved_0; /*01h */
2020 u_int8_t cmd_status; /*02h */
2021 u_int8_t reserved_1[4]; /*03h */
2022 u_int8_t sge_count; /*07h */
2023
2024 u_int32_t context; /*08h */
2025 u_int32_t pad_0; /*0Ch */
2026
2027 u_int16_t flags; /*10h */
2028 u_int16_t timeout; /*12h */
2029
2030 u_int32_t data_xfer_len; /*14h */
2031 u_int32_t opcode; /*18h */
2032
2033 union { /*1Ch */
2034 u_int8_t b[12];
2035 u_int16_t s[6];
2036 u_int32_t w[3];
2037 } mbox;
2038
2039 union mrsas_sgl sgl; /*28h */
2040 };
2041 #pragma pack()
2042
2043 #pragma pack(1)
2044 struct mrsas_abort_frame {
2045 u_int8_t cmd; /*00h */
2046 u_int8_t reserved_0; /*01h */
2047 u_int8_t cmd_status; /*02h */
2048
2049 u_int8_t reserved_1; /*03h */
2050 u_int32_t reserved_2; /*04h */
2051
2052 u_int32_t context; /*08h */
2053 u_int32_t pad_0; /*0Ch */
2054
2055 u_int16_t flags; /*10h */
2056 u_int16_t reserved_3; /*12h */
2057 u_int32_t reserved_4; /*14h */
2058
2059 u_int32_t abort_context; /*18h */
2060 u_int32_t pad_1; /*1Ch */
2061
2062 u_int32_t abort_mfi_phys_addr_lo; /*20h */
2063 u_int32_t abort_mfi_phys_addr_hi; /*24h */
2064
2065 u_int32_t reserved_5[6]; /*28h */
2066 };
2067 #pragma pack()
2068
2069 #pragma pack(1)
2070 struct mrsas_smp_frame {
2071 u_int8_t cmd; /*00h */
2072 u_int8_t reserved_1; /*01h */
2073 u_int8_t cmd_status; /*02h */
2074 u_int8_t connection_status; /*03h */
2075
2076 u_int8_t reserved_2[3]; /*04h */
2077 u_int8_t sge_count; /*07h */
2078
2079 u_int32_t context; /*08h */
2080 u_int32_t pad_0; /*0Ch */
2081
2082 u_int16_t flags; /*10h */
2083 u_int16_t timeout; /*12h */
2084
2085 u_int32_t data_xfer_len; /*14h */
2086 u_int64_t sas_addr; /*18h */
2087
2088 union {
2089 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */
2090 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */
2091 } sgl;
2092 };
2093 #pragma pack()
2094
2095
2096 #pragma pack(1)
2097 struct mrsas_stp_frame {
2098 u_int8_t cmd; /*00h */
2099 u_int8_t reserved_1; /*01h */
2100 u_int8_t cmd_status; /*02h */
2101 u_int8_t reserved_2; /*03h */
2102
2103 u_int8_t target_id; /*04h */
2104 u_int8_t reserved_3[2]; /*05h */
2105 u_int8_t sge_count; /*07h */
2106
2107 u_int32_t context; /*08h */
2108 u_int32_t pad_0; /*0Ch */
2109
2110 u_int16_t flags; /*10h */
2111 u_int16_t timeout; /*12h */
2112
2113 u_int32_t data_xfer_len; /*14h */
2114
2115 u_int16_t fis[10]; /*18h */
2116 u_int32_t stp_flags;
2117
2118 union {
2119 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */
2120 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */
2121 } sgl;
2122 };
2123 #pragma pack()
2124
2125 union mrsas_frame {
2126 struct mrsas_header hdr;
2127 struct mrsas_init_frame init;
2128 struct mrsas_io_frame io;
2129 struct mrsas_pthru_frame pthru;
2130 struct mrsas_dcmd_frame dcmd;
2131 struct mrsas_abort_frame abort;
2132 struct mrsas_smp_frame smp;
2133 struct mrsas_stp_frame stp;
2134 u_int8_t raw_bytes[64];
2135 };
2136
2137 #pragma pack(1)
2138 union mrsas_evt_class_locale {
2139
2140 struct {
2141 u_int16_t locale;
2142 u_int8_t reserved;
2143 int8_t class;
2144 } __packed members;
2145
2146 u_int32_t word;
2147
2148 } __packed;
2149
2150 #pragma pack()
2151
2152
2153 #pragma pack(1)
2154 struct mrsas_evt_log_info {
2155 u_int32_t newest_seq_num;
2156 u_int32_t oldest_seq_num;
2157 u_int32_t clear_seq_num;
2158 u_int32_t shutdown_seq_num;
2159 u_int32_t boot_seq_num;
2160
2161 } __packed;
2162
2163 #pragma pack()
2164
2165 struct mrsas_progress {
2166
2167 u_int16_t progress;
2168 u_int16_t elapsed_seconds;
2169
2170 } __packed;
2171
2172 struct mrsas_evtarg_ld {
2173
2174 u_int16_t target_id;
2175 u_int8_t ld_index;
2176 u_int8_t reserved;
2177
2178 } __packed;
2179
2180 struct mrsas_evtarg_pd {
2181 u_int16_t device_id;
2182 u_int8_t encl_index;
2183 u_int8_t slot_number;
2184
2185 } __packed;
2186
2187 struct mrsas_evt_detail {
2188
2189 u_int32_t seq_num;
2190 u_int32_t time_stamp;
2191 u_int32_t code;
2192 union mrsas_evt_class_locale cl;
2193 u_int8_t arg_type;
2194 u_int8_t reserved1[15];
2195
2196 union {
2197 struct {
2198 struct mrsas_evtarg_pd pd;
2199 u_int8_t cdb_length;
2200 u_int8_t sense_length;
2201 u_int8_t reserved[2];
2202 u_int8_t cdb[16];
2203 u_int8_t sense[64];
2204 } __packed cdbSense;
2205
2206 struct mrsas_evtarg_ld ld;
2207
2208 struct {
2209 struct mrsas_evtarg_ld ld;
2210 u_int64_t count;
2211 } __packed ld_count;
2212
2213 struct {
2214 u_int64_t lba;
2215 struct mrsas_evtarg_ld ld;
2216 } __packed ld_lba;
2217
2218 struct {
2219 struct mrsas_evtarg_ld ld;
2220 u_int32_t prevOwner;
2221 u_int32_t newOwner;
2222 } __packed ld_owner;
2223
2224 struct {
2225 u_int64_t ld_lba;
2226 u_int64_t pd_lba;
2227 struct mrsas_evtarg_ld ld;
2228 struct mrsas_evtarg_pd pd;
2229 } __packed ld_lba_pd_lba;
2230
2231 struct {
2232 struct mrsas_evtarg_ld ld;
2233 struct mrsas_progress prog;
2234 } __packed ld_prog;
2235
2236 struct {
2237 struct mrsas_evtarg_ld ld;
2238 u_int32_t prev_state;
2239 u_int32_t new_state;
2240 } __packed ld_state;
2241
2242 struct {
2243 u_int64_t strip;
2244 struct mrsas_evtarg_ld ld;
2245 } __packed ld_strip;
2246
2247 struct mrsas_evtarg_pd pd;
2248
2249 struct {
2250 struct mrsas_evtarg_pd pd;
2251 u_int32_t err;
2252 } __packed pd_err;
2253
2254 struct {
2255 u_int64_t lba;
2256 struct mrsas_evtarg_pd pd;
2257 } __packed pd_lba;
2258
2259 struct {
2260 u_int64_t lba;
2261 struct mrsas_evtarg_pd pd;
2262 struct mrsas_evtarg_ld ld;
2263 } __packed pd_lba_ld;
2264
2265 struct {
2266 struct mrsas_evtarg_pd pd;
2267 struct mrsas_progress prog;
2268 } __packed pd_prog;
2269
2270 struct {
2271 struct mrsas_evtarg_pd pd;
2272 u_int32_t prevState;
2273 u_int32_t newState;
2274 } __packed pd_state;
2275
2276 struct {
2277 u_int16_t vendorId;
2278 u_int16_t deviceId;
2279 u_int16_t subVendorId;
2280 u_int16_t subDeviceId;
2281 } __packed pci;
2282
2283 u_int32_t rate;
2284 char str[96];
2285
2286 struct {
2287 u_int32_t rtc;
2288 u_int32_t elapsedSeconds;
2289 } __packed time;
2290
2291 struct {
2292 u_int32_t ecar;
2293 u_int32_t elog;
2294 char str[64];
2295 } __packed ecc;
2296
2297 u_int8_t b[96];
2298 u_int16_t s[48];
2299 u_int32_t w[24];
2300 u_int64_t d[12];
2301 } args;
2302
2303 char description[128];
2304
2305 } __packed;
2306
2307
2308 /*******************************************************************
2309 * per-instance data
2310 ********************************************************************/
2311 struct mrsas_softc {
2312 device_t mrsas_dev; // bus device
2313 struct cdev *mrsas_cdev; // controller device
2314 uint16_t device_id; // pci device
2315 struct resource *reg_res; // register interface window
2316 int reg_res_id; // register resource id
2317 bus_space_tag_t bus_tag; // bus space tag
2318 bus_space_handle_t bus_handle; // bus space handle
2319 bus_dma_tag_t mrsas_parent_tag; // bus dma parent tag
2320 bus_dma_tag_t verbuf_tag; // verbuf tag
2321 bus_dmamap_t verbuf_dmamap; // verbuf dmamap
2322 void *verbuf_mem; // verbuf mem
2323 bus_addr_t verbuf_phys_addr; // verbuf physical addr
2324 bus_dma_tag_t sense_tag; // bus dma verbuf tag
2325 bus_dmamap_t sense_dmamap; // bus dma verbuf dmamap
2326 void *sense_mem; // pointer to sense buf
2327 bus_addr_t sense_phys_addr; // bus dma verbuf mem
2328 bus_dma_tag_t io_request_tag; // bus dma io request tag
2329 bus_dmamap_t io_request_dmamap; // bus dma io request dmamap
2330 void *io_request_mem; // bus dma io request mem
2331 bus_addr_t io_request_phys_addr; // io request physical address
2332 bus_dma_tag_t chain_frame_tag; // bus dma chain frame tag
2333 bus_dmamap_t chain_frame_dmamap; // bus dma chain frame dmamap
2334 void *chain_frame_mem; // bus dma chain frame mem
2335 bus_addr_t chain_frame_phys_addr; // chain frame phys address
2336 bus_dma_tag_t reply_desc_tag; // bus dma io request tag
2337 bus_dmamap_t reply_desc_dmamap; // bus dma io request dmamap
2338 void *reply_desc_mem; // bus dma io request mem
2339 bus_addr_t reply_desc_phys_addr; // bus dma io request mem
2340 bus_dma_tag_t ioc_init_tag; // bus dma io request tag
2341 bus_dmamap_t ioc_init_dmamap; // bus dma io request dmamap
2342 void *ioc_init_mem; // bus dma io request mem
2343 bus_addr_t ioc_init_phys_mem; // io request physical address
2344 bus_dma_tag_t data_tag; // bus dma data from OS tag
2345 struct cam_sim *sim_0; // SIM pointer
2346 struct cam_sim *sim_1; // SIM pointer
2347 struct cam_path *path_0; // ldio path pointer to CAM
2348 struct cam_path *path_1; // syspd path pointer to CAM
2349 struct mtx sim_lock; // sim lock
2350 struct mtx pci_lock; // serialize pci access
2351 struct mtx io_lock; // IO lock
2352 struct mtx ioctl_lock; // IOCTL lock
2353 struct mtx mpt_cmd_pool_lock; // lock for cmd pool linked list
2354 struct mtx mfi_cmd_pool_lock; // lock for cmd pool linked list
2355 struct mtx raidmap_lock; // lock for raid map access/update
2356 struct mtx aen_lock; // aen lock
2357 uint32_t max_fw_cmds; // Max commands from FW
2358 uint32_t max_num_sge; // Max number of SGEs
2359 struct resource *mrsas_irq; // interrupt interface window
2360 void *intr_handle; // handle
2361 int irq_id; // intr resource id
2362 struct mrsas_mpt_cmd **mpt_cmd_list;
2363 struct mrsas_mfi_cmd **mfi_cmd_list;
2364 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
2365 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
2366 bus_addr_t req_frames_desc_phys;
2367 u_int8_t *req_frames_desc;
2368 u_int8_t *req_desc;
2369 bus_addr_t io_request_frames_phys;
2370 u_int8_t *io_request_frames;
2371 bus_addr_t reply_frames_desc_phys;
2372 u_int16_t last_reply_idx;
2373 u_int32_t reply_q_depth;
2374 u_int32_t request_alloc_sz;
2375 u_int32_t reply_alloc_sz;
2376 u_int32_t io_frames_alloc_sz;
2377 u_int32_t chain_frames_alloc_sz;
2378 u_int16_t max_sge_in_main_msg;
2379 u_int16_t max_sge_in_chain;
2380 u_int8_t chain_offset_io_request;
2381 u_int8_t chain_offset_mfi_pthru;
2382 u_int32_t map_sz;
2383 u_int64_t map_id;
2384 struct mrsas_mfi_cmd *map_update_cmd;
2385 struct mrsas_mfi_cmd *aen_cmd;
2386 u_int8_t fast_path_io;
2387 void* chan;
2388 void* ocr_chan;
2389 u_int8_t adprecovery;
2390 u_int8_t remove_in_progress;
2391 u_int8_t ocr_thread_active;
2392 u_int8_t do_timedout_reset;
2393 u_int32_t reset_in_progress;
2394 u_int32_t reset_count;
2395 bus_dma_tag_t raidmap_tag[2]; // bus dma tag for RAID map
2396 bus_dmamap_t raidmap_dmamap[2]; // bus dma dmamap RAID map
2397 void *raidmap_mem[2]; // bus dma mem RAID map
2398 bus_addr_t raidmap_phys_addr[2]; // RAID map physical address
2399 bus_dma_tag_t mficmd_frame_tag; // tag for mfi frame
2400 bus_dma_tag_t mficmd_sense_tag; // tag for mfi sense
2401 bus_dma_tag_t evt_detail_tag; // event detail tag
2402 bus_dmamap_t evt_detail_dmamap; // event detail dmamap
2403 struct mrsas_evt_detail *evt_detail_mem; // event detail mem
2404 bus_addr_t evt_detail_phys_addr; // event detail physical addr
2405 bus_dma_tag_t ctlr_info_tag; // tag for get ctlr info cmd
2406 bus_dmamap_t ctlr_info_dmamap; // get ctlr info cmd dmamap
2407 void *ctlr_info_mem; // get ctlr info cmd virtual addr
2408 bus_addr_t ctlr_info_phys_addr; //get ctlr info cmd physical addr
2409 u_int32_t max_sectors_per_req;
2410 u_int32_t disableOnlineCtrlReset;
2411 atomic_t fw_outstanding;
2412 u_int32_t mrsas_debug;
2413 u_int32_t mrsas_io_timeout;
2414 u_int32_t mrsas_fw_fault_check_delay;
2415 u_int32_t io_cmds_highwater;
2416 u_int8_t UnevenSpanSupport;
2417 struct sysctl_ctx_list sysctl_ctx;
2418 struct sysctl_oid *sysctl_tree;
2419 struct proc *ocr_thread;
2420 u_int32_t last_seq_num;
2421 bus_dma_tag_t el_info_tag; // tag for get event log info cmd
2422 bus_dmamap_t el_info_dmamap; // get event log info cmd dmamap
2423 void *el_info_mem; // get event log info cmd virtual addr
2424 bus_addr_t el_info_phys_addr; //get event log info cmd physical addr
2425 struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
2426 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
2427 u_int8_t ld_ids[MRSAS_MAX_LD];
2428 struct taskqueue *ev_tq; //taskqueue for events
2429 struct task ev_task;
2430 u_int32_t CurLdCount;
2431 u_int64_t reset_flags;
2432 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
2433 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES];
2434 };
2435
2436 /* Compatibility shims for different OS versions */
2437 #if __FreeBSD_version >= 800001
2438 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2439 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2440 #define mrsas_kproc_exit(arg) kproc_exit(arg)
2441 #else
2442 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2443 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2444 #define mrsas_kproc_exit(arg) kthread_exit(arg)
2445 #endif
2446
2447 static __inline void
clear_bit(int b,volatile void * p)2448 clear_bit(int b, volatile void *p)
2449 {
2450 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2451 }
2452
2453 static __inline void
set_bit(int b,volatile void * p)2454 set_bit(int b, volatile void *p)
2455 {
2456 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2457 }
2458
2459 static __inline int
test_bit(int b,volatile void * p)2460 test_bit(int b, volatile void *p)
2461 {
2462 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
2463 }
2464
2465 #endif /* MRSAS_H */
2466