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Searched refs:WRITE_REG32 (Results 1 – 12 of 12) sorted by relevance

/freebsd-9-stable/sys/dev/qlxge/
Dqls_hw.c269 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_unicast_mac_addr()
270 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); in qls_config_unicast_mac_addr()
279 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_unicast_mac_addr()
280 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper); in qls_config_unicast_mac_addr()
289 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_unicast_mac_addr()
295 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value); in qls_config_unicast_mac_addr()
334 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_mcast_mac_addr()
335 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); in qls_config_mcast_mac_addr()
345 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); in qls_config_mcast_mac_addr()
346 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper); in qls_config_mcast_mac_addr()
[all …]
Dqls_dump.c406 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); in qls_rd_mpi_reg()
430 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); in qls_wr_mpi_reg()
432 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); in qls_wr_mpi_reg()
614 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ in qls_rd_serdes_reg()
820 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ in qls_unpause_mpi_risc()
832 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ in qls_pause_mpi_risc()
857 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); in qls_get_intr_states()
873 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); in qls_rd_xgmac_reg()
1233 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ in qls_get_probe()
1246 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ in qls_get_probe()
[all …]
Dqls_hw.h925 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) macro
932 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx))
939 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
Dqls_isr.c363 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR); in qls_mbx_isr()
/freebsd-9-stable/sys/dev/qlxgb/
Dqla_hw.h797 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\
801 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val)
804 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\
809 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\
811 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\
818 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\
825 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
Dqla_reg.h230 #define WRITE_REG32(ha, reg, val) \ macro
/freebsd-9-stable/sys/dev/qlxgbe/
Dql_misc.c70 WRITE_REG32(ha, wnd_reg, addr); in ql_rdwr_indreg32()
87 WRITE_REG32(ha, Q8_WILD_CARD, *val); in ql_rdwr_indreg32()
1320 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); in qla_ld_fw_init()
1328 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678); in qla_ld_fw_init()
1400 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); in ql_start_sequence()
1408 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678); in ql_start_sequence()
Dql_inline.h66 WRITE_REG32(ha, id_reg, id_val); in qla_sem_lock()
Dql_isr.c802 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0); in ql_mbx_isr()
920 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); in ql_mbx_isr()
921 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); in ql_mbx_isr()
Dql_hw.h205 #define WRITE_REG32(ha, reg, val) \ macro
1731 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
Dql_hw.c1448 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); in qla_mbx_cmd()
1452 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); in qla_mbx_cmd()
1497 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); in qla_mbx_cmd()
1498 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); in qla_mbx_cmd()
2916 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); in qla_confirm_9kb_enable()
2917 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); in qla_confirm_9kb_enable()
Dql_ioctl.c121 WRITE_REG32(ha, u.rv->reg, u.rv->val); in ql_eioctl()