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Searched refs:VLIW (Results 1 – 20 of 20) sorted by relevance

/freebsd-9-stable/contrib/binutils/gas/config/
Dtc-mep.h95 #define VLIW 1 macro
Dtc-mep.c947 if (mode == VLIW) in md_assemble()
1831 mode = VLIW; in mep_switch_to_vliw_mode()
1872 if (mode == VLIW) in mep_cleanup()
1879 if (mode == VLIW) in mep_flush_pending_output()
/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DR600Schedule.td10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
/freebsd-9-stable/contrib/gcc/config/mips/
Dsr71k.md15 ;; buffering is done via a VLIW dispatch style (with a packing of 6 insns);
104 ;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
/freebsd-9-stable/contrib/file/magic/Magdir/
Delf214 >18 leshort 160 STMicroelectronics 64bit VLIW DSP,
/freebsd-9-stable/contrib/gcc/config/i386/
Dpentium.md74 ;; are always issued together, much like on VLIW.
/freebsd-9-stable/contrib/llvm/include/llvm/Target/
DTargetLowering.h67 VLIW // Scheduling for VLIW targets. enumerator
/freebsd-9-stable/contrib/gcc/
Drtl.def982 after slot0 reservation for a VLIW processor. We could describe it
1026 reserved after slot1 or slot2 reservation for a VLIW processor. We
/freebsd-9-stable/contrib/gcc/config/ia64/
Ditanium1.md54 after slot0 reservation for a VLIW processor. We could describe
96 reserved after slot1 or slot2 reservation for a VLIW processor.
Ditanium2.md52 after slot0 reservation for a VLIW processor. We could describe
94 reserved after slot1 or slot2 reservation for a VLIW processor.
/freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1473 setSchedulingPreference(Sched::VLIW); in HexagonTargetLowering()
/freebsd-9-stable/contrib/gcc/doc/
Dmd.texi6665 @cindex VLIW
6668 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
6776 @acronym{VLIW} insn templates).
6928 @cindex VLIW
6931 @acronym{VLIW} processors, or more precisely, to describe a placement
6932 of small instructions into @acronym{VLIW} instruction slots. They
6962 for description that @acronym{VLIW} @samp{slot1} is reserved after
7006 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
Dtm.texi5884 combine two small instructions together on @samp{VLIW} machines).
5955 simplify the automaton pipeline description for some @acronym{VLIW}
5984 @acronym{VLIW} processor, the code could actually solve the problem of
5985 packing simple insns into the @acronym{VLIW} insn. Of course, if the
5986 rules of @acronym{VLIW} packing are described in the automaton.
7232 @var{num}. This is useful for VLIW targets, where debug info labels
Dinvoke.texi8704 previous packet. This option only has an effect when VLIW packing
8726 Pack VLIW instructions.
8731 Do not pack VLIW instructions.
8789 Run a pass to pack branches into VLIW instructions (default).
8797 Do not run a pass to pack branches into VLIW instructions.
/freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp278 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
/freebsd-9-stable/contrib/binutils/include/opcode/
DChangeLog-91031797 registers are used. Needed for VLIW optimization.
/freebsd-9-stable/contrib/binutils/gas/po/
Dgas.pot4326 msgid "VLIW packing used for -mno-pack"
4334 msgid "VLIW packing constraint violation"
7340 msgid ".vliw unavailable when VLIW is disabled."
/freebsd-9-stable/contrib/gdb/gdb/doc/
Dgdbint.texinfo2464 For example, the Renesas D10V is a 16-bit VLIW processor whose
3019 The FR-V is a VLIW architecture in which a number of RISC-like
Dgdb.info-12851 a VLIW architecture in which a number of RISC-like instructions may be
Dgdb.texinfo3383 a VLIW architecture in which a number of RISC-like instructions may be