Searched refs:UBFX (Results 1 – 9 of 9) sorted by relevance
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 103 UBFX, enumerator
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| D | AArch64InstrInfo.td | 128 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
986 // UBFIZ, UBFX
1254 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1279 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
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| D | AArch64ISelLowering.cpp | 3072 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0), in PerformANDCombine()
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 128 // BFC, BFI, UBFX, SBFX
1218 // BFI,BFC, SBFX,UBFX
1220 (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI",
1221 "(t|t2)UBFX", "(t|t2)SBFX")>;
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| D | ARMCodeEmitter.cpp | 1056 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { in emitDataProcessingInstruction()
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| D | ARMScheduleA9.td | 120 // BFC, BFI, UBFX, SBFX
2484 def : InstRW< [WriteALUsi], (instregex "BFC", "BFI", "UBFX", "SBFX")>;
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| D | ARMISelDAGToDAG.cpp | 2298 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); in SelectV6T2BitfieldExtractOp()
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| D | ARMInstrInfo.td | 3168 def UBFX : I<(outs GPR:$Rd),
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5428 case ARM::UBFX: { in validateInstruction()
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