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Searched refs:TargetRegisterInfo (Results 1 – 25 of 212) sorted by relevance

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/freebsd-9-stable/contrib/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, in TargetRegisterInfo() function in TargetRegisterInfo
34 TargetRegisterInfo::~TargetRegisterInfo() {} in ~TargetRegisterInfo()
39 else if (TargetRegisterInfo::isStackSlot(Reg)) in print()
40 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); in print()
41 else if (TargetRegisterInfo::isVirtualRegister(Reg)) in print()
42 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); in print()
78 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); in print()
87 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
111 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { in getMinimalPhysRegClass()
138 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet()
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DVirtRegMap.cpp85 if (TargetRegisterInfo::isVirtualRegister(Hint)) in hasPreferredPhys()
92 if (TargetRegisterInfo::isPhysicalRegister(Hint.second)) in hasKnownPreference()
94 if (TargetRegisterInfo::isVirtualRegister(Hint.second)) in hasKnownPreference()
100 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in assignVirt2StackSlot()
108 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in assignVirt2StackSlot()
120 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in print()
129 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in print()
157 const TargetRegisterInfo *TRI;
240 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns()
306 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg())) in rewrite()
DRegisterCoalescer.h21 class TargetRegisterInfo; variable
29 const TargetRegisterInfo &TRI;
62 CoalescerPair(const TargetRegisterInfo &tri) in CoalescerPair()
69 const TargetRegisterInfo &tri) in CoalescerPair()
DRegAllocFast.cpp58 const TargetRegisterInfo *TRI;
81 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
257 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && in killVirtReg()
267 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && in spillVirtReg()
346 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && in usePhysReg()
512 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && in allocVirtReg()
518 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || in allocVirtReg()
584 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && in defineVirtReg()
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DMachineInstr.cpp70 const TargetRegisterInfo &TRI) { in substVirtReg()
71 assert(TargetRegisterInfo::isVirtualRegister(Reg)); in substVirtReg()
79 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { in substPhysReg()
80 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in substPhysReg()
263 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; in print()
811 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || in isIdenticalTo()
812 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) in isIdenticalTo()
953 const TargetRegisterInfo *TRI) const { in getRegClassConstraint()
1001 const TargetRegisterInfo *TRI) const { in findRegisterUseOperandIdx()
1011 TargetRegisterInfo::isPhysicalRegister(MOReg) && in findRegisterUseOperandIdx()
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DInterferenceCache.h25 const TargetRegisterInfo *TRI;
112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
120 const TargetRegisterInfo *TRI,
154 const TargetRegisterInfo *);
DPeepholeOptimizer.cpp164 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
165 TargetRegisterInfo::isPhysicalRegister(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
322 TargetRegisterInfo::isPhysicalRegister(SrcReg) || in optimizeCmpInstr()
323 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
354 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, in shareSameRegisterFile()
442 if (TargetRegisterInfo::isPhysicalRegister(Def)) in optimizeCopyOrBitcast()
452 const TargetRegisterInfo &TRI = *TM->getRegisterInfo(); in optimizeCopyOrBitcast()
464 if (TargetRegisterInfo::isPhysicalRegister(Src)) in optimizeCopyOrBitcast()
482 unsigned NewVR = TargetRegisterInfo::isPhysicalRegister(Def) ? Def : in optimizeCopyOrBitcast()
512 TargetRegisterInfo::isVirtualRegister(Reg) && in isLoadFoldable()
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DDeadMachineInstructionElim.cpp32 const TargetRegisterInfo *TRI;
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in isDead()
128 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in runOnMachineFunction()
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in runOnMachineFunction()
175 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in runOnMachineFunction()
DCalcSpillWeights.cpp36 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in calculateSpillWeightsAndHints()
45 const TargetRegisterInfo &tri, in copyHint()
61 if (TargetRegisterInfo::isVirtualRegister(hreg)) in copyHint()
98 const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo(); in calculateSpillWeightAndHint()
151 if (TargetRegisterInfo::isPhysicalRegister(hint)) { in calculateSpillWeightAndHint()
DMachineCSE.cpp42 const TargetRegisterInfo *TRI;
122 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in INITIALIZE_PASS_DEPENDENCY()
132 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
206 if (TargetRegisterInfo::isVirtualRegister(Reg)) in hasLivePhysRegDefUses()
225 if (TargetRegisterInfo::isVirtualRegister(Reg)) in hasLivePhysRegDefUses()
299 if (TargetRegisterInfo::isVirtualRegister(MOReg)) in PhysRegDefsReach()
348 if (TargetRegisterInfo::isVirtualRegister(CSReg) && in isProfitableToCSE()
349 TargetRegisterInfo::isVirtualRegister(Reg)) { in isProfitableToCSE()
384 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { in isProfitableToCSE()
533 assert(TargetRegisterInfo::isVirtualRegister(OldReg) && in ProcessBlock()
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DTwoAddressInstructionPass.cpp72 const TargetRegisterInfo *TRI;
353 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); in isCopyToReg()
354 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); in isCopyToReg()
362 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) && in isPlainlyKilled()
410 if (TargetRegisterInfo::isPhysicalRegister(Reg) && in isKilled()
415 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in isKilled()
471 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); in findOnlyInterestingUse()
481 while (TargetRegisterInfo::isVirtualRegister(Reg)) { in getMappedReg()
487 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getMappedReg()
495 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible()
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DRegisterCoalescer.cpp82 const TargetRegisterInfo* TRI;
216 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, in isMoveInstr()
264 if (TargetRegisterInfo::isPhysicalRegister(Src)) { in setRegisters()
265 if (TargetRegisterInfo::isPhysicalRegister(Dst)) in setRegisters()
274 if (TargetRegisterInfo::isPhysicalRegister(Dst)) { in setRegisters()
333 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual"); in setRegisters()
334 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) && in setRegisters()
342 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) in flip()
366 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { in isCoalescable()
367 if (!TargetRegisterInfo::isPhysicalRegister(Dst)) in isCoalescable()
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/freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/
DVirtRegMap.h43 const TargetRegisterInfo *TRI;
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; } in getTargetRegInfo()
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in getPhys()
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) && in assignVirt2Phys()
107 TargetRegisterInfo::isPhysicalRegister(physReg)); in assignVirt2Phys()
117 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in clearVirt()
169 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); in getStackSlot()
DMachineInstr.h39 class TargetRegisterInfo; variable
724 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
745 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
753 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
760 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
768 const TargetRegisterInfo *TRI = NULL) const {
776 const TargetRegisterInfo *TRI = NULL) const;
781 const TargetRegisterInfo *TRI = NULL) {
794 const TargetRegisterInfo *TRI = NULL) const;
799 const TargetRegisterInfo *TRI = NULL) {
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DRegisterPressure.h43 void increase(unsigned Reg, const TargetRegisterInfo *TRI,
50 void decrease(unsigned Reg, const TargetRegisterInfo *TRI,
53 void dump(const TargetRegisterInfo *TRI) const;
216 if (TargetRegisterInfo::isVirtualRegister(Reg))
222 if (TargetRegisterInfo::isVirtualRegister(Reg))
228 if (TargetRegisterInfo::isVirtualRegister(Reg))
252 const TargetRegisterInfo *TRI;
438 const TargetRegisterInfo *TRI);
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp55 const TargetRegisterInfo *TRI) const { in storeRegToStackSlot()
57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot()
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot()
83 const TargetRegisterInfo *TRI) const { in loadRegFromStackSlot()
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
DMLxExpansionPass.cpp51 const TargetRegisterInfo *TRI;
90 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
100 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
106 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
118 if (TargetRegisterInfo::isPhysicalRegister(Reg) || in getDefReg()
129 if (TargetRegisterInfo::isPhysicalRegister(Reg) || in getDefReg()
144 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in hasLoopHazard()
158 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { in hasLoopHazard()
166 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in hasLoopHazard()
172 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in hasLoopHazard()
/freebsd-9-stable/contrib/llvm/include/llvm/Target/
DTargetRegisterInfo.h219 class TargetRegisterInfo : public MCRegisterInfo {
232 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
238 virtual ~TargetRegisterInfo();
829 const TargetRegisterInfo *TRI,
862 return TargetRegisterInfo::virtReg2Index(Reg); in operator()
879 const TargetRegisterInfo *TRI;
883 explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0,
905 const TargetRegisterInfo *TRI;
908 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) in PrintRegUnit()
922 PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri) in PrintVRegOrUnit()
DTargetInstrInfo.h37 class TargetRegisterInfo; variable
62 const TargetRegisterInfo *TRI,
210 const TargetRegisterInfo &TRI) const;
505 const TargetRegisterInfo *TRI) const { in storeRegToStackSlot()
518 const TargetRegisterInfo *TRI) const { in loadRegFromStackSlot()
631 const TargetRegisterInfo *TRI) const { in getLdStBaseRegImmOfs()
957 const TargetRegisterInfo *TRI) const { in getPartialRegUpdateClearance()
977 const TargetRegisterInfo *TRI) const { in getUndefRegClearance()
1001 const TargetRegisterInfo *TRI) const {} in breakPartialRegDependency()
/freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp144 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
145 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
195 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
196 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
217 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
218 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
253 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { in runOnMachineFunction()
/freebsd-9-stable/contrib/llvm/lib/Target/Mips/
DMipsInstrInfo.h90 const TargetRegisterInfo *TRI) const { in storeRegToStackSlot()
98 const TargetRegisterInfo *TRI) const { in loadRegFromStackSlot()
106 const TargetRegisterInfo *TRI,
113 const TargetRegisterInfo *TRI,
/freebsd-9-stable/contrib/llvm/lib/Target/XCore/
DXCoreInstrInfo.h35 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo()
74 const TargetRegisterInfo *TRI) const;
80 const TargetRegisterInfo *TRI) const;
/freebsd-9-stable/contrib/llvm/lib/Target/MSP430/
DMSP430InstrInfo.h53 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo()
65 const TargetRegisterInfo *TRI) const;
70 const TargetRegisterInfo *TRI) const;
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64FrameLowering.h68 const TargetRegisterInfo *TRI) const;
72 const TargetRegisterInfo *TRI) const;
92 const TargetRegisterInfo *TRI,
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrInfo.h195 const TargetRegisterInfo &TRI) const;
256 const TargetRegisterInfo *TRI) const;
269 const TargetRegisterInfo *TRI) const;
373 const TargetRegisterInfo *TRI) const;
375 const TargetRegisterInfo *TRI) const;
377 const TargetRegisterInfo *TRI) const;

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