| /freebsd-9-stable/contrib/llvm/lib/ExecutionEngine/Interpreter/ |
| D | Execution.cpp | 50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
53 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
64 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
75 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
86 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
97 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
119 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
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| /freebsd-9-stable/contrib/llvm/lib/Target/R600/ |
| D | R600ExpandSpecialInstrs.cpp | 215 unsigned Src1 = BMI->getOperand( in runOnMachineFunction() local
219 (void) Src1; in runOnMachineFunction()
221 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
222 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
266 unsigned Src1 = 0; in runOnMachineFunction() local
272 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction()
278 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
283 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
318 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 345 const MachineOperand &Src1 = MI->getOperand(Src1Idx); in verifyInstruction() local
346 if (Src1.isImm() || Src1.isFPImm()) { in verifyInstruction()
447 MachineOperand &Src1 = MI->getOperand(Src1Idx); in legalizeOperands() local
458 if (ReadsVCC && Src1.isReg() && in legalizeOperands()
459 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { in legalizeOperands()
466 if (Src1.isImm() || Src1.isFPImm() || in legalizeOperands()
467 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) { in legalizeOperands()
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| D | R600InstrInfo.cpp | 1231 MachineOperand &Src1 = MI->getOperand( in buildSlotOfVectorInstruction() local
1234 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg()); in buildSlotOfVectorInstruction()
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| D | R600Instructions.td | 1502 // Src1 = Offset
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| /freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 160 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
162 EVT PtrVT = Src1.getValueType(); in emitCLC()
172 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
175 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
194 SDValue Src1, SDValue Src2, SDValue Size, in EmitTargetCodeForMemcmp() argument
200 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
250 SDValue Src1, SDValue Src2, in EmitTargetCodeForStrcmp() argument
253 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue); in EmitTargetCodeForStrcmp()
254 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
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| D | SystemZSelectionDAGInfo.h | 45 SDValue Src1, SDValue Src2, SDValue Size,
63 SDValue Src1, SDValue Src2,
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| /freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 159 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() local
161 if (Src1.getImm() != 0) in runOnMachineFunction()
176 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() local
181 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
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| D | HexagonISelDAGToDAG.cpp | 1328 SDNode* Src1 = N->getOperand(0).getNode(); in SelectAdd() local
1329 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse() in SelectAdd()
1330 || Src1->getValueType(0) != MVT::i32) { in SelectAdd()
1338 Src1->getOperand(0), in SelectAdd()
1339 Src1->getOperand(1)); in SelectAdd()
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| /freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 2999 SDValue Src1 = getValue(I.getOperand(0)); in visitShuffleVector() local
3008 EVT SrcVT = Src1.getValueType(); in visitShuffleVector()
3012 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3028 VT, Src1, Src2)); in visitShuffleVector()
3036 VT, Src2, Src1)); in visitShuffleVector()
3043 bool Src1U = Src1.getOpcode() == ISD::UNDEF; in visitShuffleVector()
3049 MOps1[0] = Src1; in visitShuffleVector()
3052 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
3068 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3124 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
[all …]
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| D | LegalizeVectorTypes.cpp | 1190 SDValue Src1 = N->getOperand(2); in SplitVecOp_VSELECT() local
1206 llvm::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL); in SplitVecOp_VSELECT()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2683 SDValue Src1 = Op.getOperand(0); in LowerADDC_ADDE_SUBC_SUBE() local
2684 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2685 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
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| /freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6709 unsigned Src1 = MI->getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
6724 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); in EmitInstrWithCustomInserter()
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