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Searched refs:SchedRW (Results 1 – 15 of 15) sorted by relevance

/freebsd-9-stable/contrib/llvm/utils/TableGen/
DCodeGenSchedule.cpp410 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence() local
411 if (!SchedRW.IsSequence) { in expandRWSequence()
416 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
418 for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end(); in expandRWSequence()
492 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead)); in findOrInsertRW() local
494 SchedReads.push_back(SchedRW); in findOrInsertRW()
496 SchedWrites.push_back(SchedRW); in findOrInsertRW()
969 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
992 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead); in mutuallyExclusive() local
993 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant"); in mutuallyExclusive()
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/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrSystem.td16 let SchedRW = [WriteSystem] in {
39 } // SchedRW
48 let SchedRW = [WriteSystem] in {
71 } // SchedRW
77 let SchedRW = [WriteSystem] in {
121 } // SchedRW
126 let SchedRW = [WriteSystem] in {
136 } // SchedRW
141 let SchedRW = [WriteSystem] in {
151 } // SchedRW
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DX86InstrInfo.td846 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
859 let SchedRW = [WriteALU] in {
869 } // SchedRW
876 let mayLoad = 1, SchedRW = [WriteLoad] in {
893 } // mayLoad, SchedRW
895 let mayStore = 1, SchedRW = [WriteStore] in {
922 } // mayStore, SchedRW
926 let mayLoad = 1, SchedRW = [WriteLoad] in {
933 } // mayLoad, SchedRW
934 let mayStore = 1, SchedRW = [WriteStore] in {
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DX86InstrControl.td23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
49 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
63 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
91 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
151 let SchedRW = [WriteJump] in {
206 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
237 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
271 SchedRW = [WriteJump] in {
DX86InstrArithmetic.td17 let SchedRW = [WriteLEA] in {
39 } // SchedRW
153 let isCommutable = 1, SchedRW = [WriteIMul] in {
172 } // isCommutable, SchedRW
175 let SchedRW = [WriteIMulLd, ReadAfterLd] in {
197 } // SchedRW
204 let SchedRW = [WriteIMul] in {
243 } // SchedRW
246 let SchedRW = [WriteIMulLd] in {
288 } // SchedRW
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DX86InstrShiftRotate.td18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
65 } // Constraints = "$src = $dst", SchedRW
68 let SchedRW = [WriteShiftLd, WriteRMW] in {
122 } // SchedRW
124 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
168 } // Constraints = "$src = $dst", SchedRW
171 let SchedRW = [WriteShiftLd, WriteRMW] in {
222 } // SchedRW
224 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
280 } // Constraints = "$src = $dst", SchedRW
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DX86SchedHaswell.td74 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
78 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
82 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
DX86SchedSandyBridge.td69 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
73 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
77 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
DX86InstrFPStack.td425 let mayLoad = 1, SchedRW = [WriteLoad] in {
439 let mayStore = 1, SchedRW = [WriteStore] in {
484 let mayStore = 1, SchedRW = [WriteStore] in {
494 let SchedRW = [WriteMove] in {
521 let SchedRW = [WriteZero] in {
527 let SchedRW = [WriteFAdd] in {
534 } // SchedRW
537 let SchedRW = [WriteFAdd] in {
575 } // SchedRW
578 let SchedRW = [WriteALU] in {
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DX86InstrMMX.td247 let SchedRW = [WriteMove] in {
257 } // SchedRW
259 let SchedRW = [WriteLoad] in {
269 } // SchedRW
271 let SchedRW = [WriteMove] in {
297 } // SchedRW
592 let SchedRW = [WriteShuffle] in {
DX86InstrCMovSetCC.td19 isCommutable = 1, SchedRW = [WriteALU] in {
41 SchedRW = [WriteALULd, ReadAfterLd] in {
DX86InstrCompiler.td154 let SchedRW = [WriteSystem] in {
192 } // SchedRW
255 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
318 let SchedRW = [WriteMicrocoded] in {
381 } // SchedRW
609 SchedRW = [WriteALULd, WriteRMW] in {
697 SchedRW = [WriteALULd, WriteRMW] in {
731 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
752 SchedRW = [WriteALULd, WriteRMW] in {
759 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
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DX86InstrSSE.td401 isPseudo = 1, SchedRW = [WriteZero] in {
418 isPseudo = 1, SchedRW = [WriteZero] in {
435 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
473 isPseudo = 1, SchedRW = [WriteZero] in {
849 let SchedRW = [WriteStore] in {
882 } // SchedRW
885 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
941 let SchedRW = [WriteStore] in {
958 } // SchedRW
961 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
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/freebsd-9-stable/contrib/llvm/include/llvm/Target/
DTargetSchedule.td90 // that have a scheduling class (itinerary class or SchedRW list)
168 list<SchedReadWrite> SchedRW = schedrw;
DTarget.td421 list<SchedReadWrite> SchedRW;