| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 253 case ISD::SUBE: in selectNode()
258 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 237 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
616 case ISD::SUBE: { in selectNode()
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| D | MipsSEISelLowering.cpp | 138 setTargetDAGCombine(ISD::SUBE); in MipsSETargetLowering()
980 case ISD::SUBE: in PerformDAGCombine()
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| /freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 ADDE, SUBE, enumerator
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| /freebsd-9-stable/contrib/llvm/patches/ |
| D | patch-r262261-llvm-r198281-sparc.diff | 78 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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| D | patch-r262261-llvm-r198286-sparc.diff | 119 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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| D | patch-r262261-llvm-r198157-sparc.diff | 214 + defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1403 setOperationAction(ISD::SUBE, MVT::i8, Expand); in HexagonTargetLowering()
1404 setOperationAction(ISD::SUBE, MVT::i16, Expand); in HexagonTargetLowering()
1405 setOperationAction(ISD::SUBE, MVT::i32, Expand); in HexagonTargetLowering()
1406 setOperationAction(ISD::SUBE, MVT::i64, Expand); in HexagonTargetLowering()
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 84 SUBE, // Sub using carry enumerator
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| D | ARMISelLowering.cpp | 663 setOperationAction(ISD::SUBE, MVT::i32, Custom); in ARMTargetLowering()
1049 case ARMISD::SUBE: return "ARMISD::SUBE"; in getTargetNodeName()
5955 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
6157 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
10729 case ARMISD::SUBE: in computeMaskedBitsForTargetNode()
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| D | ARMInstrInfo.td | 159 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
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| /freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 206 case ISD::SUBE: return "sube"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1156 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1556 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1605 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| D | DAGCombiner.cpp | 1131 case ISD::SUBE: return visitSUBE(N); in visit()
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| /freebsd-9-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 100 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1462 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
2702 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2703 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2836 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
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| D | SparcInstrInfo.td | 478 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
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| /freebsd-9-stable/contrib/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
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| /freebsd-9-stable/contrib/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 95 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
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| /freebsd-9-stable/contrib/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 432 setOperationAction(ISD::SUBE, VT, Custom); in resetOperationActions()
13335 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
13476 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
13542 case ISD::SUBE: in ReplaceNodeResults()
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