| /freebsd-9-stable/contrib/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 82 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
95 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
96 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
97 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
98 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
99 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
100 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
101 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
102 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
103 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
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| D | X86TargetTransformInfo.cpp | 471 { ISD::SETCC, MVT::v2f64, 1 }, in getCmpSelInstrCost()
472 { ISD::SETCC, MVT::v4f32, 1 }, in getCmpSelInstrCost()
473 { ISD::SETCC, MVT::v2i64, 1 }, in getCmpSelInstrCost()
474 { ISD::SETCC, MVT::v4i32, 1 }, in getCmpSelInstrCost()
475 { ISD::SETCC, MVT::v8i16, 1 }, in getCmpSelInstrCost()
476 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
480 { ISD::SETCC, MVT::v4f64, 1 }, in getCmpSelInstrCost()
481 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
483 { ISD::SETCC, MVT::v4i64, 4 }, in getCmpSelInstrCost()
484 { ISD::SETCC, MVT::v8i32, 4 }, in getCmpSelInstrCost()
[all …]
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| D | X86ISelLowering.cpp | 520 setOperationAction(ISD::SETCC , MVT::i8 , Custom); in resetOperationActions()
521 setOperationAction(ISD::SETCC , MVT::i16 , Custom); in resetOperationActions()
522 setOperationAction(ISD::SETCC , MVT::i32 , Custom); in resetOperationActions()
523 setOperationAction(ISD::SETCC , MVT::f32 , Custom); in resetOperationActions()
524 setOperationAction(ISD::SETCC , MVT::f64 , Custom); in resetOperationActions()
525 setOperationAction(ISD::SETCC , MVT::f80 , Custom); in resetOperationActions()
528 setOperationAction(ISD::SETCC , MVT::i64 , Custom); in resetOperationActions()
849 setOperationAction(ISD::SETCC, VT, Expand); in resetOperationActions()
959 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in resetOperationActions()
960 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in resetOperationActions()
[all …]
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| D | X86ISelLowering.h | 95 SETCC, enumerator
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| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 125 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
126 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
127 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
128 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
243 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
324 setOperationAction(ISD::SETCC, MVT::v8i8, Custom); in AArch64TargetLowering()
325 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in AArch64TargetLowering()
326 setOperationAction(ISD::SETCC, MVT::v4i16, Custom); in AArch64TargetLowering()
327 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); in AArch64TargetLowering()
328 setOperationAction(ISD::SETCC, MVT::v2i32, Custom); in AArch64TargetLowering()
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| D | AArch64ISelLowering.h | 81 SETCC, enumerator
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| /freebsd-9-stable/contrib/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 113 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
114 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering()
144 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
633 if (Intr->getOpcode() == ISD::SETCC) { in LowerBRCOND()
762 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); in LowerSELECT_CC()
864 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), in PerformDAGCombine()
870 case ISD::SETCC: { in PerformDAGCombine()
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| D | R600ISelLowering.cpp | 63 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
64 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
78 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
79 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
817 ISD::SETCC, in LowerFPTOUINT()
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| /freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 339 SETCC, enumerator
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| D | SelectionDAG.h | 665 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
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| /freebsd-9-stable/contrib/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
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| D | MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
113 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
196 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 32 SETCC, enumerator
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| /freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
313 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); in ScalarizeVecRes_SETCC()
340 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_VSETCC()
518 case ISD::SETCC: in SplitVectorResult()
1138 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
1442 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
1443 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
1505 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; in WidenVectorResult()
2260 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT, in WidenVecRes_SETCC()
2315 return DAG.getNode(ISD::SETCC, SDLoc(N), in WidenVecRes_VSETCC()
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| D | LegalizeVectorOps.cpp | 222 case ISD::SETCC: in LegalizeOp()
299 else if (Node->getOpcode() == ISD::SETCC) in LegalizeOp()
764 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
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| D | DAGCombiner.cpp | 577 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1159 case ISD::SETCC: return visitSETCC(N); in visit()
2715 TLI.isOperationLegal(ISD::SETCC, in visitAND()
3238 TLI.isOperationLegal(ISD::SETCC, in visitOR()
3477 case ISD::SETCC: in visitXOR()
4258 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
4302 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
4332 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
4385 if (SCC.getOpcode() == ISD::SETCC) in visitSELECT_CC()
4424 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
[all …]
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| D | TargetLowering.cpp | 205 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
210 NewLHS = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
1227 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
1333 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
1376 if (N0.getOpcode() == ISD::SETCC && in SimplifySetCC()
1426 Op0.getOperand(0).getOpcode() == ISD::SETCC && in SimplifySetCC()
1427 Op0.getOperand(1).getOpcode() == ISD::SETCC) { in SimplifySetCC()
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| D | LegalizeDAG.cpp | 1198 case ISD::SETCC: in LegalizeOp()
1201 Node->getOpcode() == ISD::SETCC ? 2 : 1; in LegalizeOp()
3629 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
3677 if (Tmp2.getOpcode() == ISD::SETCC) { in ExpandNode()
3694 case ISD::SETCC: { in ExpandNode()
3705 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), in ExpandNode()
3876 Node->getOpcode() == ISD::SETCC) { in PromoteNode()
4016 case ISD::SETCC: { in PromoteNode()
4025 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), in PromoteNode()
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| D | SelectionDAGDumper.cpp | 185 case ISD::SETCC: return "setcc"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; in PromoteIntegerResult()
794 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; in PromoteIntegerOperand()
2486 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; in ExpandIntegerOperand()
2588 Tmp2 = DAG.getNode(ISD::SETCC, dl, in IntegerExpandSetCCOperands()
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| D | LegalizeFloatTypes.cpp | 631 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; in SoftenFloatOperand()
1284 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; in ExpandFloatOperand()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 228 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in MipsTargetLowering()
242 setOperationAction(ISD::SETCC, MVT::f32, Custom); in MipsTargetLowering()
243 setOperationAction(ISD::SETCC, MVT::f64, Custom); in MipsTargetLowering()
490 if (Op.getOpcode() != ISD::SETCC) in createFPCmp()
528 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
728 case ISD::SETCC: return lowerSETCC(Op, DAG); in LowerOperation()
1420 SDValue Cond = DAG.getNode(ISD::SETCC, DL, in lowerSELECT_CC()
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| D | MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::SETCC); in MipsSETargetLowering()
199 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
236 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
901 if (Op0->getOpcode() != ISD::SETCC) in performVSELECTCombine()
995 case ISD::SETCC: in PerformDAGCombine()
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| /freebsd-9-stable/contrib/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1292 case ICmp: return ISD::SETCC; in InstructionOpcodeToISD()
1293 case FCmp: return ISD::SETCC; in InstructionOpcodeToISD()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1439 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1440 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1441 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1442 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1466 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
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