| /freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2047 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
2050 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
2055 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
2056 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
2073 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
2074 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
2124 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
2131 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, &ScalarRes[0], NumElts); in ReplaceLoadVector()
2154 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
2156 if (ResVT.isVector()) { in ReplaceINTRINSIC_W_CHAIN()
[all …]
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| /freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1219 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1225 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1231 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1451 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
1457 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
1463 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
2497 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
2501 ResVT, WideSETCC, DAG.getConstant(0, in WidenVecOp_SETCC()
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| D | LegalizeIntegerTypes.cpp | 168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
170 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
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| D | DAGCombiner.cpp | 7855 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
7856 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
7859 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
7873 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
7879 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
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| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1009 EVT ResVT = N->getValueType(0); in SelectVTBL() local
1010 bool is64BitRes = ResVT.is64BitVector(); in SelectVTBL()
1023 return CurDAG->getMachineNode(Opc, dl, ResVT, Ops); in SelectVTBL()
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| /freebsd-9-stable/contrib/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2286 EVT ResVT = RVLocs[i].getValVT(); in DoSelectCall() local
2287 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in DoSelectCall()
2288 unsigned MemSize = ResVT.getSizeInBits()/8; in DoSelectCall()
2293 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in DoSelectCall()
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| D | X86ISelLowering.cpp | 6149 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
6151 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
6152 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
6156 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
6157 if(ResVT.is256BitVector()) in LowerAVXCONCAT_VECTORS()
6158 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
6160 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
7893 MVT ResVT = Op.getSimpleValueType(); in LowerEXTRACT_SUBVECTOR() local
7897 if (ResVT.is128BitVector() && in LowerEXTRACT_SUBVECTOR()
7902 if (ResVT.is256BitVector() && InVT.is512BitVector() && in LowerEXTRACT_SUBVECTOR()
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| /freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4712 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
4729 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
4732 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
4741 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
4749 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
4762 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
4765 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
4772 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
4778 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
4784 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
[all …]
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| /freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 1679 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
1681 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
1697 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
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