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Searched refs:Register (Results 1 – 25 of 238) sorted by relevance

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/freebsd-9-stable/contrib/llvm/include/llvm/MC/
DMachineLocation.h28 unsigned Register; // gcc/gdb register number. variable
37 : IsRegister(false), Register(0), Offset(0) {} in MachineLocation()
40 : IsRegister(true), Register(R), Offset(0) {} in MachineLocation()
43 : IsRegister(false), Register(R), Offset(O) {} in MachineLocation()
46 return IsRegister == Other.IsRegister && Register == Other.Register &&
54 unsigned getReg() const { return Register; } in getReg()
57 void setRegister(unsigned R) { Register = R; } in setRegister()
62 Register = R; in set()
68 Register = R; in set()
DMCDwarf.h300 unsigned Register; variable
308 : Operation(Op), Label(L), Register(R), Offset(O), in MCCFIInstruction()
314 : Operation(Op), Label(L), Register(R1), Register2(R2) { in MCCFIInstruction()
321 static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, in createDefCfa() argument
323 return MCCFIInstruction(OpDefCfa, L, Register, -Offset, ""); in createDefCfa()
328 static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register) { in createDefCfaRegister() argument
329 return MCCFIInstruction(OpDefCfaRegister, L, Register, 0, ""); in createDefCfaRegister()
348 static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, in createOffset() argument
350 return MCCFIInstruction(OpOffset, L, Register, Offset, ""); in createOffset()
356 static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, in createRelOffset() argument
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DMCStreamer.h615 virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);
617 virtual void EmitCFIDefCfaRegister(int64_t Register);
618 virtual void EmitCFIOffset(int64_t Register, int64_t Offset);
623 virtual void EmitCFISameValue(int64_t Register);
624 virtual void EmitCFIRestore(int64_t Register);
625 virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);
629 virtual void EmitCFIUndefined(int64_t Register);
640 virtual void EmitWin64EHPushReg(unsigned Register);
641 virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);
643 virtual void EmitWin64EHSaveReg(unsigned Register, unsigned Offset);
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DMCWin64EH.h34 unsigned Register; variable
37 : Operation(Op), Label(L), Offset(0), Register(Reg) { in MCWin64EHInstruction()
44 : Operation(Op), Label(L), Offset(Off), Register(Reg) { in MCWin64EHInstruction()
59 unsigned getRegister() const { return Register; } in getRegister()
/freebsd-9-stable/contrib/llvm/lib/MC/
DMCAsmStreamer.cpp64 void EmitRegisterName(int64_t Register);
218 virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);
220 virtual void EmitCFIDefCfaRegister(int64_t Register);
221 virtual void EmitCFIOffset(int64_t Register, int64_t Offset);
226 virtual void EmitCFISameValue(int64_t Register);
227 virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);
230 virtual void EmitCFIUndefined(int64_t Register);
241 virtual void EmitWin64EHPushReg(unsigned Register);
242 virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);
244 virtual void EmitWin64EHSaveReg(unsigned Register, unsigned Offset);
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DMCStreamer.cpp286 void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { in EmitCFIDefCfa() argument
289 MCCFIInstruction::createDefCfa(Label, Register, Offset); in EmitCFIDefCfa()
310 void MCStreamer::EmitCFIDefCfaRegister(int64_t Register) { in EmitCFIDefCfaRegister() argument
313 MCCFIInstruction::createDefCfaRegister(Label, Register); in EmitCFIDefCfaRegister()
318 void MCStreamer::EmitCFIOffset(int64_t Register, int64_t Offset) { in EmitCFIOffset() argument
321 MCCFIInstruction::createOffset(Label, Register, Offset); in EmitCFIOffset()
326 void MCStreamer::EmitCFIRelOffset(int64_t Register, int64_t Offset) { in EmitCFIRelOffset() argument
329 MCCFIInstruction::createRelOffset(Label, Register, Offset); in EmitCFIRelOffset()
364 void MCStreamer::EmitCFISameValue(int64_t Register) { in EmitCFISameValue() argument
367 MCCFIInstruction::createSameValue(Label, Register); in EmitCFISameValue()
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/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DR600RegisterInfo.td2 class R600Reg <string name, bits<16> encoding> : Register<name> {
8 Register <name> {
19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
26 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
45 [!cast<Register>("T"#Index#"_X"),
46 !cast<Register>("T"#Index#"_Y"),
47 !cast<Register>("T"#Index#"_Z"),
48 !cast<Register>("T"#Index#"_W")],
52 [!cast<Register>("T"#Index#"_X"),
53 !cast<Register>("T"#Index#"_Y")],
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DSIRegisterInfo.td1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
14 class SIReg <string n, bits<16> encoding = 0> : Register<n> {
142 // Register classes used as source and destination
151 // Register class for all scalar registers (SGPRs + Special Registers)
168 // Register class for all vector registers (VGPRs + Interploation Registers)
/freebsd-9-stable/contrib/llvm/lib/Target/Mips/
DMipsRegisterInfo.td1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
30 class MipsReg<bits<16> Enc, string n> : Register<n> {
35 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
45 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
54 class AFPR<bits<16> Enc, string n, list<Register> subregs>
60 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
67 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
73 class ACCReg<bits<16> Enc, string n, list<Register> subregs>
209 def PC : Register<"pc">;
217 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
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/freebsd-9-stable/sys/dev/acpica/Osd/
DOsdHardware.c88 AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value, in AcpiOsReadPciConfiguration() argument
99 PciId->Function, Register, Width / 8); in AcpiOsReadPciConfiguration()
106 AcpiOsWritePciConfiguration (ACPI_PCI_ID *PciId, UINT32 Register, in AcpiOsWritePciConfiguration() argument
116 pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register, in AcpiOsWritePciConfiguration()
/freebsd-9-stable/contrib/llvm/include/llvm/Target/
DTargetCallingConv.td71 class CCAssignToReg<list<Register> regList> : CCAction {
72 list<Register> RegList = regList;
77 class CCAssignToRegWithShadow<list<Register> regList,
78 list<Register> shadowList> : CCAction {
79 list<Register> RegList = regList;
80 list<Register> ShadowRegList = shadowList;
94 class CCAssignToStackWithShadow<int size, int align, Register reg> :
96 Register ShadowReg = reg;
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td1 //===- AArch64RegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
37 class AArch64Reg<bits<16> enc, string n> : Register<n> {
42 class AArch64RegWithSubs<bits<16> enc, string n, list<Register> subregs = [],
64 [!cast<Register>("W"#Index)], [sub_32]>,
133 [!cast<Register>("B" # Index)], [sub_8]>,
137 [!cast<Register>("H" # Index)], [sub_16]>,
141 [!cast<Register>("S" # Index)], [sub_32]>,
145 [!cast<Register>("D" # Index)], [sub_64]>,
197 def NZCV : Register<"nzcv"> {
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp309 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass() local
310 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR64RegisterClass()
320 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); in DecodeGPR64xspRegisterClass() local
321 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR64xspRegisterClass()
331 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass() local
332 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR32RegisterClass()
342 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); in DecodeGPR32wspRegisterClass() local
343 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR32wspRegisterClass()
353 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); in DecodeFPR8RegisterClass() local
354 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR8RegisterClass()
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/freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp305 struct Register { struct in __anon793ee23e0111::SystemZAsmParser
311 bool parseRegister(Register &Reg);
313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
443 bool SystemZAsmParser::parseRegister(Register &Reg) { in parseRegister()
484 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group, in parseRegister()
507 Register Reg; in parseRegister()
537 Register Reg; in parseAddress()
553 Register Reg; in parseAddress()
611 Register Reg; in ParseRegister()
679 Register Reg; in parseOperand()
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/freebsd-9-stable/contrib/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td1 //===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===//
14 class XCoreReg<string n> : Register<n> {
43 // Register classes.
/freebsd-9-stable/contrib/llvm/lib/CodeGen/
DStackMaps.cpp84 assert(Loc.LocType == Location::Register && in recordStackMapOpers()
150 assert(Locations[i].LocType == Location::Register && in recordPatchPoint()
260 case Location::Register: in serializeToStackMapSection()
292 if (Loc.LocType == Location::Register) { in serializeToStackMapSection()
301 assert(Loc.LocType != Location::Register && in serializeToStackMapSection()
/freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
16 class HexagonReg<string n> : Register<n> {
20 class HexagonDoubleReg<string n, list<Register> subregs> :
38 class Rd<bits<5> num, string n, list<Register> subregs> :
141 // Register classes.
/freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.td1 //===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
14 class NVPTXReg<string n> : Register<n> {
50 // Register classes
/freebsd-9-stable/contrib/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===//
14 class SparcReg<bits<16> Enc, string n> : Register<n> {
19 class SparcCtrlReg<string n>: Register<n> {
38 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
45 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
181 // Register classes.
195 // Register class for 64-bit mode, with a 64-bit spill slot size.
/freebsd-9-stable/contrib/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.td1 //===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===//
14 class MSP430Reg<bits<4> num, string n> : Register<n> {
19 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMScheduleV6.td104 // Register offset
117 // Register offset with update
157 // Register offset
170 // Register offset with update
195 // FP Special Register to Integer Register File Move
DARMRegisterInfo.td1 //===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
15 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
23 class ARMFReg<bits<16> Enc, string n> : Register<n> {
158 // Current Program Status Register.
182 // Register classes.
185 // lr == Link Register
189 // r9 == May be reserved as Thread Register
325 // Register class representing a pair of consecutive D registers.
341 // Register class representing a pair of even-odd GPRs.
/freebsd-9-stable/contrib/binutils/gas/doc/
Dc-sh.texi73 * SH-Regs:: Register Names
94 @subsection Register Names
137 Register direct
140 Register indirect
143 Register indirect with pre-decrement
146 Register indirect with post-increment
149 Register indirect with displacement
152 Register indexed
/freebsd-9-stable/contrib/llvm/lib/MC/MCParser/
DAsmParser.cpp335 bool parseRegisterOrRegisterNumber(int64_t &Register, SMLoc DirectiveLoc);
2780 bool AsmParser::parseRegisterOrRegisterNumber(int64_t &Register, in parseRegisterOrRegisterNumber() argument
2787 Register = getContext().getRegisterInfo()->getDwarfRegNum(RegNo, true); in parseRegisterOrRegisterNumber()
2789 return parseAbsoluteExpression(Register); in parseRegisterOrRegisterNumber()
2797 int64_t Register = 0; in parseDirectiveCFIDefCfa() local
2798 if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) in parseDirectiveCFIDefCfa()
2809 getStreamer().EmitCFIDefCfa(Register, Offset); in parseDirectiveCFIDefCfa()
2864 int64_t Register = 0; in parseDirectiveCFIDefCfaRegister() local
2865 if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) in parseDirectiveCFIDefCfaRegister()
2868 getStreamer().EmitCFIDefCfaRegister(Register); in parseDirectiveCFIDefCfaRegister()
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/freebsd-9-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r200617-sparc.diff49 // Register the MC asm info.
55 // Register the MC codegen info.

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