| /freebsd-9-stable/contrib/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
65 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
67 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
76 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
84 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 227 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
317 unsigned RegNum; member
390 return Reg.RegNum; in getReg()
395 return Reg.RegNum; in getPtrReg()
427 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() argument
429 Op->Reg.RegNum = RegNum; in CreateReg()
435 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreatePtrReg() argument
437 Op->Reg.RegNum = RegNum; in CreatePtrReg()
473 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); in addRegAsmOperands()
1087 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber() argument
[all …]
|
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 130 bool TryParseVector(uint32_t &RegNum, SMLoc &RegEndLoc, StringRef &Layout,
143 IdentifyRegister(unsigned &RegNum, SMLoc &RegEndLoc, StringRef &LayoutSpec,
189 unsigned RegNum; member
200 unsigned RegNum; member
247 return Reg.RegNum; in getReg()
860 static AArch64Operand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() argument
862 Op->Reg.RegNum = RegNum; in CreateReg()
866 static AArch64Operand *CreateWrappedReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateWrappedReg() argument
868 Op->Reg.RegNum = RegNum; in CreateWrappedReg()
890 static AArch64Operand *CreateVectorList(unsigned RegNum, unsigned Count, in CreateVectorList() argument
[all …]
|
| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 195 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); in printSavedRegsBitmask() local
197 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
203 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
210 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); in printSavedRegsBitmask() local
211 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 156 unsigned RegNum; member
201 return Reg.RegNum; in getReg()
295 static SparcOperand *CreateReg(unsigned RegNum, in CreateReg() argument
299 Op->Reg.RegNum = RegNum; in CreateReg()
320 Op->Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
343 Op->Reg.RegNum = Reg; in MorphToQuadReg()
|
| /freebsd-9-stable/contrib/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 381 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
384 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
388 int getSEHRegNum(unsigned RegNum) const;
|
| /freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.h | 58 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const;
|
| D | NVPTXRegisterInfo.cpp | 116 int NVPTXRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
|
| D | NVPTXAsmPrinter.cpp | 380 unsigned RegNum = RegMap[Reg]; in encodeVirtualRegister() local
402 Ret |= (RegNum & 0x0FFFFFFF); in encodeVirtualRegister()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 65 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
|
| D | X86CodeEmitter.cpp | 1480 unsigned RegNum = getX86RegNum(MO.getReg()) << 4; in emitInstruction() local
1482 RegNum |= 1 << 7; in emitInstruction()
1490 RegNum |= Val; in emitInstruction()
1493 emitConstant(RegNum, 1); in emitInstruction()
|
| D | X86RegisterInfo.cpp | 89 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { in getCompactUnwindRegNum() argument
90 switch (getLLVMRegNum(RegNum, isEH)) { in getCompactUnwindRegNum()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 376 unsigned RegNum; member
381 unsigned RegNum; member
410 unsigned RegNum; member
569 return Reg.RegNum; in getReg()
1271 .contains(VectorList.RegNum)); in isVecListDPair()
1287 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1314 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
1541 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local
1542 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1912 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
[all …]
|
| /freebsd-9-stable/contrib/llvm/tools/clang/lib/Basic/ |
| D | TargetInfo.cpp | 324 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in isValidGCCRegisterName()
377 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in getNormalizedGCCRegisterName()
|
| /freebsd-9-stable/contrib/llvm/patches/ |
| D | patch-r262261-llvm-r198484-sparc.diff | 310 + unsigned RegNum;
345 + return Reg.RegNum;
439 + static SparcOperand *CreateReg(unsigned RegNum,
443 + Op->Reg.RegNum = RegNum;
|
| D | patch-r262261-llvm-r199033-sparc.diff | 393 static SparcOperand *CreateReg(unsigned RegNum,
398 Op->Reg.RegNum = RegNum;
414 + Op->Reg.RegNum = DoubleRegs[regIdx / 2];
437 + Op->Reg.RegNum = Reg;
|
| /freebsd-9-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDILCFGStructurizer.cpp | 232 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
234 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
511 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, in insertCondBranchBefore() argument
517 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchBefore()
522 int NewOpcode, int RegNum) { in insertCondBranchEnd() argument
527 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchEnd()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.h | 37 void printRegName(raw_ostream &O, unsigned RegNum) const;
|
| /freebsd-9-stable/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1419 unsigned RegNum = GetX86RegNum(MO) << 4; in EncodeInstruction() local
1421 RegNum |= 1 << 7; in EncodeInstruction()
1429 RegNum |= Val; in EncodeInstruction()
1432 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, in EncodeInstruction()
|
| /freebsd-9-stable/contrib/llvm/tools/clang/include/clang/Basic/ |
| D | TargetInfo.h | 592 const unsigned RegNum; member
|
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 562 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); in MergeLDR_STR() local
568 ((isNotVFP && RegNum > PRegNum) || in MergeLDR_STR()
569 ((Count < Limit) && RegNum == PRegNum+1)) && in MergeLDR_STR()
574 PRegNum = RegNum; in MergeLDR_STR()
|
| D | ARMCodeEmitter.cpp | 1302 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); in emitLoadStoreMultipleInstruction() local
1304 RegNum < 16); in emitLoadStoreMultipleInstruction()
1305 Binary |= 0x1 << RegNum; in emitLoadStoreMultipleInstruction()
|
| /freebsd-9-stable/contrib/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1282 unsigned RegNum = Registers[i]->EnumValue; in computeUberSets() local
1283 if (AllocatableRegs.count(RegNum)) in computeUberSets()
1286 UberSetIDs.join(0, RegNum); in computeUberSets()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 988 if (unsigned RegNum = MO2.getReg()) { in printThumbAddrModeRROperand() local
990 printRegName(O, RegNum); in printThumbAddrModeRROperand()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1867 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
1873 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
1874 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
1895 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
1899 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
1900 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
|