Searched refs:RADEON_VCLK_ECP_CNTL (Results 1 – 4 of 4) sorted by relevance
526 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()529 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()579 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()582 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()732 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()736 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()768 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()772 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()819 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()823 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()[all …]
921 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()993 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()
655 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect()663 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect()706 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()
1787 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ macro