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Searched refs:RADEON_CRTC2_GEN_CNTL (Results 1 – 7 of 7) sorted by relevance

/freebsd-9-stable/sys/dev/drm2/radeon/
Dradeon_legacy_encoders.c1051 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_legacy_tv_dac_dpms()
1113 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in radeon_legacy_tv_dac_dpms()
1313 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in r300_legacy_tv_detect()
1322 WREG32(RADEON_CRTC2_GEN_CNTL, in r300_legacy_tv_detect()
1365 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in r300_legacy_tv_detect()
1453 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_legacy_ext_dac_detect()
1478 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | in radeon_legacy_ext_dac_detect()
1519 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in radeon_legacy_ext_dac_detect()
1590 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_legacy_tv_dac_detect()
1607 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in radeon_legacy_tv_dac_detect()
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Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
345 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
510 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; in radeon_crtc_do_set_base()
631 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; in radeon_set_crtc_timing()
655 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in radeon_set_crtc_timing()
Dradeon_cursor.c86 reg = RADEON_CRTC2_GEN_CNTL; in radeon_hide_cursor()
115 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); in radeon_show_cursor()
Dradeon_bios.c551 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
573 WREG32(RADEON_CRTC2_GEN_CNTL,
598 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
Dr100.c91 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { in r100_wait_for_vblank()
432 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_prepare()
434 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in r100_pm_prepare()
463 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_finish()
465 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in r100_pm_finish()
Dradeon_device.c462 RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_card_posted()
Dradeon_reg.h452 #define RADEON_CRTC2_GEN_CNTL 0x03f8 macro