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Searched refs:R4 (Results 1 – 25 of 66) sorted by relevance

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/freebsd-9-stable/contrib/wpa/src/crypto/
Dsha1-internal.c156 #define R4(v,w,x,y,z,i) \ macro
214 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
215 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
216 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
217 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
218 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/freebsd-9-stable/contrib/bind9/lib/isc/
Dsha1.c121 #define R4(v,w,x,y,z,i) \ macro
146 #define nR4(v,w,x,y,z,i) R4(*v,*w,*x,*y,*z,i)
245 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in transform()
246 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in transform()
247 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in transform()
248 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in transform()
249 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in transform()
/freebsd-9-stable/contrib/ntp/lib/isc/
Dsha1.c119 #define R4(v,w,x,y,z,i) \ macro
144 #define nR4(v,w,x,y,z,i) R4(*v,*w,*x,*y,*z,i)
243 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in transform()
244 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in transform()
245 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in transform()
246 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in transform()
247 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in transform()
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMFrameLowering.cpp182 case ARM::R4: in emitPrologue()
318 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
321 TII.get(ARM::t2BICri), ARM::R4) in emitPrologue()
322 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
325 .addReg(ARM::R4, RegState::Kill)); in emitPrologue()
415 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && in emitEpilogue()
417 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
421 .addReg(ARM::R4)); in emitEpilogue()
783 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
790 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
[all …]
DARMCallingConv.td98 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
99 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
194 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
202 R5, R4, (sequence "D%u", 15, 8),
206 // Also save R7-R4 first to match the stack frame fixed spill areas.
207 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
209 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
DThumb1FrameLowering.cpp123 case ARM::R4: in emitPrologue()
278 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && in emitEpilogue()
280 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
284 .addReg(ARM::R4)); in emitEpilogue()
DARMBaseRegisterInfo.h42 case R4: case R5: case R6: case R7: in isARMArea1Register()
/freebsd-9-stable/contrib/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
DXCoreRegisterInfo.cpp65 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td20 CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
30 CCIfType<[f32, i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
DHexagonVarargsCallingConvention.h53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, in CC_Hexagon32_VarArgs()
109 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, in RetCC_Hexagon32_VarArgs()
DHexagonRegisterInfo.td68 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
105 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
/freebsd-9-stable/contrib/llvm/include/llvm/Support/
DMathExtras.h230 #define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16) macro
231 #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
/freebsd-9-stable/contrib/gdb/gdb/
Drs6000-tdep.c2146 #define R4(name) { STR(name), 4, 4, 0, 0 } macro
2199 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
2203 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
2214 /* 87 */ R4(pvr), \
2219 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2222 /* 116 */ R4(dec), R(dabr), R4(ear)
2230 /*151*/R4(vscr), R4(vrsave)
2251 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2252 /* 71 */ R4(fpscr)
Ddpx2-nat.c39 R0, R1, R2, R3, R4, R5, R6, R7,
/freebsd-9-stable/contrib/file/magic/Magdir/
Dpkgadd4 # pkgadd: file(1) magic for SysV R4 PKG Datastreams
Derlang7 # OTP R3-R4
/freebsd-9-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r198910-sparc.diff212 ; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]]
213 ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]]
261 ; abs64: add %[[R3]], %hm(G), %[[R4:[gilo][0-7]]]
262 ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]]
Dpatch-r262261-llvm-r199028-sparc.diff67 ; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]]
68 ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]]
Dpatch-r262261-llvm-r199775-sparc.diff192 ; v8abs: ld [%[[R4]]]
/freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/
DPPCCallingConv.td28 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
81 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
/freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td311 bits<4> R4;
315 let Inst{11-8} = R4;
733 let R4 = 0;
738 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2, uimm8zx4:$R4),
739 mnemonic#"\t$R1, $R3, $R2, $R4", []>;
749 let R4 = 0;
761 let R4 = 0;
773 let R4 = 0;
921 let R4 = 0;
929 let R4 = 0;
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h213 case R4: case R5: case R6: case R7: in isARMLowRegister()
/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DAMDILRegisterInfo.td26 def R4 : AMDILReg<4, "r4">, DwarfRegNum<[4]>;
/freebsd-9-stable/contrib/nvi/build/
Dconfig.guess126 m88k:*:4*:R4*)

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