| /freebsd-9-stable/contrib/llvm/patches/ |
| D | patch-r262261-llvm-r198592-sparc.diff | 20 - SP::Q5, SP::Q13, -1, -1,
28 + SP::Q5, SP::Q13, (unsigned)-1, (unsigned)-1,
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| D | patch-r262261-llvm-r199031-sparc.diff | 20 - SP::Q5, SP::Q13, (unsigned)-1, (unsigned)-1,
28 + SP::Q5, SP::Q13, ~0U, ~0U,
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| D | patch-r262261-llvm-r199974-sparc.diff | 49 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
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| D | patch-r262261-llvm-r198484-sparc.diff | 273 + Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
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| D | patch-r262261-llvm-r198591-sparc.diff | 343 + SP::Q5, SP::Q13, -1, -1,
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| /freebsd-9-stable/lib/msun/src/ |
| D | s_expm1.c | 127 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
184 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
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| /freebsd-9-stable/lib/msun/bsdsrc/ |
| D | b_tgamma.c | 107 #define Q5 5.12449347980666221336054633184e-03 macro
254 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 112 SP::Q5, SP::Q13, ~0U, ~0U,
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 169 def Q5 : Rq<20, "F20", [D10, D11]>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 91 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
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| D | ARMRegisterInfo.td | 143 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
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| D | ARMInstrInfo.td | 5131 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
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| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConv.td | 77 CCIfType<[f128], CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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| D | AArch64ISelLowering.cpp | 1022 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 119 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 429 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: in getMachineOpValue()
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| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1678 .Case("v5", IsVec128 ? AArch64::Q5 : AArch64::D5) in IdentifyRegister()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3024 case ARM::Q5: return ARM::D10; in getDRegFromQReg()
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| /freebsd-9-stable/contrib/tzdata/ |
| D | northamerica | 1190 # http://www.nrc-cnrc.gc.ca/eng/services/time/faq/index.html#Q5
|