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Searched refs:OpVT (Results 1 – 16 of 16) sorted by relevance

/freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/
DRuntimeLibcalls.h393 Libcall getFPEXT(EVT OpVT, EVT RetVT);
397 Libcall getFPROUND(EVT OpVT, EVT RetVT);
401 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
405 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
409 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
413 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
/freebsd-9-stable/contrib/llvm/lib/CodeGen/
DTargetLoweringBase.cpp411 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
412 if (OpVT == MVT::f32) { in getFPEXT()
417 } else if (OpVT == MVT::f64) { in getFPEXT()
427 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { in getFPROUND() argument
429 if (OpVT == MVT::f64) in getFPROUND()
431 if (OpVT == MVT::f80) in getFPROUND()
433 if (OpVT == MVT::f128) in getFPROUND()
435 if (OpVT == MVT::ppcf128) in getFPROUND()
438 if (OpVT == MVT::f80) in getFPROUND()
440 if (OpVT == MVT::f128) in getFPROUND()
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrFMA.td119 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
127 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
134 (OpVT (OpNode RC:$src2, RC:$src1,
159 SDNode OpNode, RegisterClass RC, ValueType OpVT,
164 x86memop, RC, OpVT, mem_frag>;
166 x86memop, RC, OpVT, mem_frag>;
170 x86memop, RC, OpVT, mem_frag, OpNode>,
201 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
209 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
DX86InstrAVX512.td435 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
440 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
446 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
452 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
457 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
504 ValueType OpVT, ValueType SrcVT> {
521 X86MemOperand x86memop, ValueType OpVT> {
527 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
534 (OpVT (OpNode (mem_frag addr:$src1),
546 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
[all …]
DX86ISelLowering.cpp6708 static SDValue getVZextMovL(MVT VT, MVT OpVT, in getVZextMovL() argument
6718 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; in getVZextMovL()
6724 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; in getVZextMovL()
6726 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, in getVZextMovL()
6728 OpVT, in getVZextMovL()
6736 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, in getVZextMovL()
6738 OpVT, SrcOp))); in getVZextMovL()
7858 MVT OpVT = Op.getSimpleValueType(); in LowerSCALAR_TO_VECTOR() local
7862 if (!OpVT.is128BitVector()) { in LowerSCALAR_TO_VECTOR()
7864 unsigned SizeFactor = OpVT.getSizeInBits()/128; in LowerSCALAR_TO_VECTOR()
[all …]
DX86InstrSSE.td2768 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2777 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2784 [(set RC:$dst, (OpVT (OpNode RC:$src1,
5157 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5166 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5174 (OpVT (OpNode RC:$src1,
6668 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6677 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6684 (OpVT (OpNode RC:$src1,
7070 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2229 EVT OpVT = Op.getOperand(0).getValueType(); in LowerSINT_TO_FP() local
2230 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2232 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2236 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { in LowerSINT_TO_FP()
2237 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2244 if (!TLI.isTypeLegal(OpVT)) in LowerSINT_TO_FP()
2249 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2278 EVT OpVT = Op.getOperand(0).getValueType(); in LowerUINT_TO_FP() local
2279 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2283 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
[all …]
/freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp469 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
470 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
471 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
DLegalizeDAG.cpp1203 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType(); in LegalizeOp() local
1206 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
1212 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
1621 MVT OpVT = LHS.getSimpleValueType(); in LegalizeSetCCCondCode() local
1624 switch (TLI.getCondCodeAction(CCCode, OpVT)) { in LegalizeSetCCCondCode()
1631 if (TLI.isCondCodeLegal(InvCC, OpVT)) { in LegalizeSetCCCondCode()
1641 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT) in LegalizeSetCCCondCode()
1646 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT) in LegalizeSetCCCondCode()
1663 if (!OpVT.isInteger()) { in LegalizeSetCCCondCode()
1683 if (TLI.isCondCodeLegal(InvCC, OpVT)) { in LegalizeSetCCCondCode()
[all …]
DLegalizeTypes.cpp274 EVT OpVT = N->getOperand(i).getValueType(); in run() local
275 switch (getTypeAction(OpVT)) { in run()
DDAGCombiner.cpp6536 EVT OpVT = N0.getValueType(); in visitSINT_TO_FP() local
6547 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
6548 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
6593 EVT OpVT = N0.getValueType(); in visitUINT_TO_FP() local
6604 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
6605 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
9274 EVT OpVT = Ops[0].getValueType(); in visitINSERT_VECTOR_ELT() local
9275 if (InVal.getValueType() != OpVT) in visitINSERT_VECTOR_ELT()
9276 InVal = OpVT.bitsGT(InVal.getValueType()) ? in visitINSERT_VECTOR_ELT()
9277 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in visitINSERT_VECTOR_ELT()
[all …]
DTargetLowering.cpp1110 EVT OpVT = Val.getValueType(); in ValueHasExactlyOneBitSet() local
1111 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); in ValueHasExactlyOneBitSet()
DSelectionDAGBuilder.cpp6211 MVT OpVT = MVT::Other; in visitInlineAsm() local
6226 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo)); in visitInlineAsm()
6229 OpVT = TLI->getSimpleValueType(CS.getType()); in visitInlineAsm()
6250 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD). in visitInlineAsm()
6254 OpInfo.ConstraintVT = OpVT; in visitInlineAsm()
/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DR600ISelLowering.cpp1584 EVT OpVT = Ops[0].getValueType(); in PerformDAGCombine() local
1585 if (InVal.getValueType() != OpVT) in PerformDAGCombine()
1586 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
1587 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in PerformDAGCombine()
1588 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); in PerformDAGCombine()
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMISelLowering.cpp3731 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN() local
3733 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3734 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
3741 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3742 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
3748 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
3749 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
3754 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, in LowerFCOPYSIGN()
3755 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
3757 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, in LowerFCOPYSIGN()
[all …]
/freebsd-9-stable/contrib/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp1591 MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i]; in ApplyTypeConstraints() local
1593 MadeChange |= getChild(i+1)->UpdateNodeType(0, OpVT, TP); in ApplyTypeConstraints()