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Searched refs:OpSize (Results 1 – 22 of 22) sorted by relevance

/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrSystem.td67 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
83 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
93 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
103 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
113 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
119 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
170 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
177 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
184 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
191 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
[all …]
DX86InstrShiftRotate.td25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
42 OpSize;
58 "shl{w}\t$dst", [], IIC_SR>, OpSize;
78 OpSize;
94 OpSize;
113 OpSize;
131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
146 IIC_SR>, OpSize;
161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
179 OpSize;
[all …]
DX86InstrFormats.td115 class OpSize { bit hasOpSizePrefix = 1; }
371 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
381 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
390 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
433 // PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain.
434 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
436 // VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
438 // VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
439 // S2I - SSE2 scalar instructions with TB and OpSize prefixes.
459 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
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DX86InstrVMX.td20 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
23 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
27 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
30 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
35 "vmclear\t$vmcs", []>, OpSize, TB;
DX86InstrControl.td29 [], IIC_RET>, OpSize;
35 [], IIC_RET_IMM>, OpSize;
39 "{l}ret{w|f}", [], IIC_RET>, OpSize;
45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
132 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
142 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
182 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
189 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
199 "callw\t$dst", []>, OpSize;
DX86InstrInfo.td849 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
878 IIC_POP_REG16>, OpSize;
882 IIC_POP_REG>, OpSize;
884 IIC_POP_MEM>, OpSize;
890 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
897 IIC_PUSH_REG>, OpSize;
901 IIC_PUSH_REG>, OpSize;
904 OpSize;
913 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
918 OpSize;
[all …]
DX86InstrExtension.td17 "{cbtw|cbw}", [], IIC_CBW>, OpSize; // AX = signext(AL)
24 "{cwtd|cwd}", [], IIC_CBW>, OpSize; // DX:AX = signext(AX)
45 TB, OpSize, Sched<[WriteALU]>;
49 TB, OpSize, Sched<[WriteALULd]>;
71 TB, OpSize, Sched<[WriteALU]>;
75 TB, OpSize, Sched<[WriteALULd]>;
DX86InstrArithmetic.td21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
71 [], IIC_MUL16_REG>, OpSize, Sched<[WriteIMul]>;
98 [], IIC_MUL16_MEM>, OpSize, SchedLoadReg<WriteIMulLd>;
118 IIC_IMUL16_RR>, OpSize, Sched<[WriteIMul]>;
136 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize,
160 TB, OpSize;
182 TB, OpSize;
211 IIC_IMUL16_RRI>, OpSize;
218 OpSize;
253 OpSize;
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DX86InstrSSE.td816 TB, OpSize, VEX;
822 TB, OpSize, VEX;
829 TB, OpSize, VEX, VEX_L;
835 TB, OpSize, VEX, VEX_L;
841 TB, OpSize;
847 TB, OpSize;
1149 itin, SSEPackedDouble>, TB, OpSize,
2115 // SSE2 instructions without OpSize prefix
2382 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2387 "comisd">, TB, OpSize, VEX, VEX_LIG;
[all …]
DX86InstrCMovSetCC.td25 IIC_CMOV16_RR>,TB,OpSize;
47 TB, OpSize;
DX86InstrAVX512.td796 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
977 VEX_4V, VEX_L, OpSize, TB;
1020 VEX, OpSize, TA, VEX_W;
1090 OpSize, EVEX_V512, VEX_W,
1097 OpSize, EVEX_V512, VEX_W,
1107 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1116 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1283 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1291 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1690 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
[all …]
DX86InstrMMX.td530 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
536 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
539 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
DX86InstrCompiler.td324 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
336 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
354 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
369 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
622 [], IIC_ALU_NONMEM>, OpSize, LOCK;
648 [], IIC_ALU_MEM>, OpSize, LOCK;
669 [], IIC_ALU_MEM>, OpSize, LOCK;
704 [], IIC_UNARY_MEM>, OpSize, LOCK;
739 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
786 itin>, OpSize;
DX86CodeEmitter.cpp690 if (TSFlags & X86II::OpSize) in emitOpcodePrefix()
879 if (TSFlags & X86II::OpSize) in emitVEXOpcodePrefix()
DX86ISelLowering.cpp2731 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall() local
2732 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in LowerCall()
/freebsd-9-stable/contrib/llvm/lib/Analysis/
DTargetTransformInfo.cpp288 unsigned OpSize = OpTy->getScalarSizeInBits(); in getOperationCost() local
289 if (DL->isLegalInteger(OpSize) && in getOperationCost()
290 OpSize <= DL->getPointerTypeSizeInBits(Ty)) in getOperationCost()
DConstantFolding.cpp601 unsigned OpSize = DL->getTypeSizeInBits(Op0->getType()); in SymbolicallyEvaluateBinop() local
606 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) - in SymbolicallyEvaluateBinop()
607 Offs2.zextOrTrunc(OpSize)); in SymbolicallyEvaluateBinop()
/freebsd-9-stable/contrib/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h303 OpSize = 1 << 6, enumerator
DX86MCCodeEmitter.cpp617 if (TSFlags & X86II::OpSize) in EmitVEXOpcodePrefix()
1112 if (TSFlags & X86II::OpSize) in EmitOpcodePrefix()
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1450 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() : in LowerCall() local
1452 OpSize = (OpSize + 7) / 8; in LowerCall()
1454 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in LowerCall()
/freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp10978 int64_t OpSize; in GatherAllAliases() local
10984 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, in GatherAllAliases()
10993 OpPtr, OpSize, OpIsVolatile, OpSrcValue, OpSrcValueOffset, in GatherAllAliases()
/freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3076 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; in CalculateTailCallArgDest() local
3077 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in CalculateTailCallArgDest()