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Searched refs:OpNode (Results 1 – 25 of 32) sorted by relevance

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/freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h78 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
80 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
82 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
85 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td169 multiclass I3<string OpcStr, SDNode OpNode> {
172 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
176 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
179 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
183 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
190 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
193 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
197 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
201 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
DNVPTXVector.td241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
245 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
248 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
252 [(set regclass1:$dst, (OpNode regclass1:$a, regclass2:$b))],
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
259 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
261 multiclass IntBinVOp<string asmstr, SDNode OpNode,
264 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
266 def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
268 def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
[all …]
DNVPTXISelDAGToDAG.cpp2335 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { in SelectADDRsi_imp() argument
2349 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr, in SelectADDRsi() argument
2351 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32); in SelectADDRsi()
2355 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr, in SelectADDRsi64() argument
2357 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64); in SelectADDRsi64()
2362 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { in SelectADDRri_imp() argument
2391 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr, in SelectADDRri() argument
2393 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32); in SelectADDRri()
2397 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr, in SelectADDRri64() argument
2399 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64); in SelectADDRri64()
/freebsd-9-stable/contrib/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
264 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
268 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
274 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
278 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
284 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
288 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
298 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
304 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
[all …]
DMipsInstrFPU.td93 SDPatternOperator OpNode= null_frag> :
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
101 SDPatternOperator OpNode = null_frag> {
102 def _D32 : ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
104 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>,
111 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
113 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
117 SDPatternOperator OpNode= null_frag> {
118 def _D32 : ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
120 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
[all …]
DMipsMSAInstrInfo.td1129 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1136 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1140 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1147 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1151 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1158 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1162 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1169 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1174 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1180 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
[all …]
DMipsInstrInfo.td410 SDPatternOperator OpNode = null_frag>:
413 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
422 SDPatternOperator OpNode = null_frag> :
425 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
450 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
454 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
457 SDPatternOperator OpNode = null_frag>:
460 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
471 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
474 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
[all …]
DMicroMipsInstrInfo.td30 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
34 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
40 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
44 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMips16InstrInfo.td1301 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1302 Mips16Pat<(OpNode CPU16Regs:$r),
1308 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1309 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1321 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1322 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1331 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1332 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1339 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1340 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrFMA.td120 SDPatternOperator OpNode = null_frag> {
127 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
134 (OpVT (OpNode RC:$src2, RC:$src1,
159 SDNode OpNode, RegisterClass RC, ValueType OpVT,
170 x86memop, RC, OpVT, mem_frag, OpNode>,
177 SDNode OpNode> {
178 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
180 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
201 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
209 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
[all …]
DX86InstrAVX512.td520 SDNode OpNode, PatFrag mem_frag,
527 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
534 (OpVT (OpNode (mem_frag addr:$src1),
612 SDNode OpNode, ValueType vt> {
617 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
687 SDNode OpNode, ValueType vt> {
691 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
696 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
722 SDNode OpNode, ValueType vt, Operand CC, string asm,
726 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
[all …]
DX86InstrFPStack.td130 multiclass FPBinary_rr<SDNode OpNode> {
134 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
136 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
138 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
143 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
148 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
152 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
156 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
160 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
164 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
[all …]
DX86InstrCMovSetCC.td82 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
86 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
90 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
DX86InstrSSE.td187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
232 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
241 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
248 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
492 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
498 [(set VR128:$dst, (vt (OpNode VR128:$src1,
510 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
513 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
[all …]
/freebsd-9-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r198740-sparc.diff99 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
103 - [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
106 - [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
109 + [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
112 + [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
Dpatch-r262261-llvm-r198893-sparc.diff64 +multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
69 + [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
73 + [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
77 +multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
82 + [(OpNode Ty:$rd, ADDRrr:$addr)]>;
86 + [(OpNode Ty:$rd, ADDRri:$addr)]>;
Dpatch-r262261-llvm-r198157-sparc.diff136 -multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
137 +multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
143 - [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
144 + [(set Ty:$dst, (OpNode Ty:$b, Ty:$c))]>;
149 - [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
150 + [(set Ty:$dst, (OpNode Ty:$b, (Ty simm13:$c)))]>;
/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMInstrNEON.td2331 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2334 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2337 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2340 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2396 ValueType TyD, ValueType TyQ, SDNode OpNode>
2399 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2414 ValueType TyQ, ValueType TyD, SDNode OpNode>
2417 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2443 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2447 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/XCore/
DXCoreInstrInfo.td208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
214 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
225 SDNode OpNode> {
228 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
231 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
237 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
246 SDNode OpNode> {
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]
/freebsd-9-stable/contrib/llvm/lib/Target/Sparc/
DSparcInstrFormats.td197 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
201 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
204 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
DSparcInstrInfo.td230 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
254 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
259 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
263 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
267 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
272 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
276 [(OpNode Ty:$rd, ADDRri:$addr)]>;
/freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td20 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
23 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
27 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
33 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
40 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
46 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
53 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
57 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
63 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
[all …]
/freebsd-9-stable/contrib/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp2791 TreePatternNode *OpNode = InVal->clone(); in parseInstructionPattern() local
2794 OpNode->clearPredicateFns(); in parseInstructionPattern()
2797 if (Record *Xform = OpNode->getTransformFn()) { in parseInstructionPattern()
2798 OpNode->setTransformFn(0); in parseInstructionPattern()
2800 Children.push_back(OpNode); in parseInstructionPattern()
2801 OpNode = new TreePatternNode(Xform, Children, OpNode->getNumTypes()); in parseInstructionPattern()
2804 ResultNodeOperands.push_back(OpNode); in parseInstructionPattern()
3265 TreePatternNode *OpNode = DstPattern->getChild(ii); in ParsePatterns() local
3266 if (Record *Xform = OpNode->getTransformFn()) { in ParsePatterns()
3267 OpNode->setTransformFn(0); in ParsePatterns()
[all …]

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