Searched refs:NumVecs (Results 1 – 5 of 5) sorted by relevance
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 117 SDNode *SelectVTBL(SDNode *N, unsigned NumVecs, bool IsExt);
120 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
124 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
141 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
147 unsigned NumVecs, const uint16_t *Opcodes);
671 unsigned NumVecs, in SelectVLD() argument
673 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
702 if (NumVecs == 1) in SelectVLD()
704 else if (NumVecs == 3) in SelectVLD()
708 is64BitVector ? NumVecs : NumVecs * 2); in SelectVLD()
[all …]
|
| D | AArch64ISelLowering.cpp | 3604 unsigned NumVecs = 0; in CombineBaseUpdate() local
3610 NumVecs = 1; break; in CombineBaseUpdate()
3612 NumVecs = 2; break; in CombineBaseUpdate()
3614 NumVecs = 3; break; in CombineBaseUpdate()
3616 NumVecs = 4; break; in CombineBaseUpdate()
3618 NumVecs = 1; isLoad = false; break; in CombineBaseUpdate()
3620 NumVecs = 2; isLoad = false; break; in CombineBaseUpdate()
3622 NumVecs = 3; isLoad = false; break; in CombineBaseUpdate()
3624 NumVecs = 4; isLoad = false; break; in CombineBaseUpdate()
3626 NumVecs = 2; break; in CombineBaseUpdate()
[all …]
|
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1041 unsigned NumVecs; in DecodeVLDSTPostInstruction() local
1045 NumVecs = 4; break; in DecodeVLDSTPostInstruction()
1048 NumVecs = 3; break; in DecodeVLDSTPostInstruction()
1050 NumVecs = 1; break; in DecodeVLDSTPostInstruction()
1053 NumVecs = 2; break; in DecodeVLDSTPostInstruction()
1060 switch (NumVecs) { in DecodeVLDSTPostInstruction()
1085 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8))); in DecodeVLDSTPostInstruction()
1091 switch (NumVecs) { in DecodeVLDSTPostInstruction()
1127 unsigned NumVecs = 0; in DecodeVLDSTLanePostInstruction() local
1146 NumVecs = 1; in DecodeVLDSTLanePostInstruction()
[all …]
|
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 216 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
224 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
232 bool isUpdating, unsigned NumVecs,
238 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
244 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
276 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1657 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs, in GetVLDSTAlign() argument
1659 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1660 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1778 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
[all …]
|
| D | ARMISelLowering.cpp | 9355 unsigned NumVecs = 0; in CombineBaseUpdate() local
9361 NumVecs = 1; break; in CombineBaseUpdate()
9363 NumVecs = 2; break; in CombineBaseUpdate()
9365 NumVecs = 3; break; in CombineBaseUpdate()
9367 NumVecs = 4; break; in CombineBaseUpdate()
9369 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
9371 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
9373 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
9375 NumVecs = 1; isLoad = false; break; in CombineBaseUpdate()
9377 NumVecs = 2; isLoad = false; break; in CombineBaseUpdate()
[all …]
|