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Searched refs:MRM5r (Results 1 – 9 of 9) sorted by relevance

/freebsd-9-stable/contrib/llvm/utils/TableGen/
DX86RecognizableInstr.cpp63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
804 case X86Local::MRM5r: in emitInstructionSpecifier()
922 case X86Local::MRM5r: in emitDecodePath()
965 case X86Local::MRM5r: in emitDecodePath()
1039 case X86Local::MRM5r: in emitDecodePath()
1103 case X86Local::MRM5r: in emitDecodePath()
/freebsd-9-stable/contrib/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h265 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
632 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp868 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1345 case X86II::MRM4r: case X86II::MRM5r: in EncodeInstruction()
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86InstrShiftRotate.td126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
140 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86CodeEmitter.cpp1062 case X86II::MRM4r: case X86II::MRM5r: in emitVEXOpcodePrefix()
1358 case X86II::MRM4r: case X86II::MRM5r: in emitInstruction()
DX86InstrArithmetic.td113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
117 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
121 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
125 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
1227 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
DX86InstrInfo.td1434 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1437 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1439 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1972 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
DX86InstrSystem.td359 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
DX86InstrFormats.td26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;