1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35 * 36 * machConst.h -- 37 * 38 * Machine dependent constants. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * 55 * $FreeBSD: stable/9/sys/mips/include/cpuregs.h 219693 2011-03-16 08:22:29Z jmallett $ 56 */ 57 58 #ifndef _MIPS_CPUREGS_H_ 59 #define _MIPS_CPUREGS_H_ 60 61 /* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: 64 * 65 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 66 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 67 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 68 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 69 * 70 * Caching of mapped addresses is controlled by bits in the TLB entry. 71 */ 72 73 #define MIPS_KSEG0_LARGEST_PHYS (0x20000000) 74 #define MIPS_KSEG0_PHYS_MASK (0x1fffffff) 75 #define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ 76 #define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) 77 78 #ifndef LOCORE 79 #define MIPS_KUSEG_START 0x00000000 80 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) 81 #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) 82 #define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) 83 #define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) 84 #define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) 85 #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) 86 #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) 87 #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) 88 #define MIPS_KSEG2_START MIPS_KSSEG_START 89 #define MIPS_KSEG2_END MIPS_KSSEG_END 90 #endif 91 92 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 93 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 94 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 95 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 96 97 #define MIPS_IS_KSEG0_ADDR(x) \ 98 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 99 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 100 #define MIPS_IS_KSEG1_ADDR(x) \ 101 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 102 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 103 #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 104 MIPS_IS_KSEG1_ADDR(x)) 105 106 /* 107 * Cache Coherency Attributes: 108 * UC: Uncached. 109 * UA: Uncached accelerated. 110 * C: Cacheable, coherency unspecified. 111 * CNC: Cacheable non-coherent. 112 * CC: Cacheable coherent. 113 * CCE: Cacheable coherent, exclusive read. 114 * CCEW: Cacheable coherent, exclusive write. 115 * CCUOW: Cacheable coherent, update on write. 116 * 117 * Note that some bits vary in meaning across implementations (and that the 118 * listing here is no doubt incomplete) and that the optimal cached mode varies 119 * between implementations. 0x02 is required to be UC and 0x03 is required to 120 * be a least C. 121 * 122 * We define the following logical bits: 123 * UNCACHED: 124 * The optimal uncached mode for the target CPU type. This must 125 * be suitable for use in accessing memory-mapped devices. 126 * CACHED: The optional cached mode for the target CPU type. 127 */ 128 129 #define MIPS_CCA_UC 0x02 /* Uncached. */ 130 #define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */ 131 132 #if defined(CPU_R4000) || defined(CPU_R10000) 133 #define MIPS_CCA_CNC 0x03 134 #define MIPS_CCA_CCE 0x04 135 #define MIPS_CCA_CCEW 0x05 136 137 #ifdef CPU_R4000 138 #define MIPS_CCA_CCUOW 0x06 139 #endif 140 141 #ifdef CPU_R10000 142 #define MIPS_CCA_UA 0x07 143 #endif 144 145 #define MIPS_CCA_CACHED MIPS_CCA_CCEW 146 #endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 147 148 #if defined(CPU_SB1) 149 #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 150 #endif 151 152 #ifndef MIPS_CCA_UNCACHED 153 #define MIPS_CCA_UNCACHED MIPS_CCA_UC 154 #endif 155 156 /* 157 * If we don't know which cached mode to use and there is a cache coherent 158 * mode, use it. If there is not a cache coherent mode, use the required 159 * cacheable mode. 160 */ 161 #ifndef MIPS_CCA_CACHED 162 #ifdef MIPS_CCA_CC 163 #define MIPS_CCA_CACHED MIPS_CCA_CC 164 #else 165 #define MIPS_CCA_CACHED MIPS_CCA_C 166 #endif 167 #endif 168 169 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 170 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 171 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 172 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) 173 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 174 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) 175 176 #define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) 177 178 #define MIPS_XKPHYS_START 0x8000000000000000 179 #define MIPS_XKPHYS_END 0xbfffffffffffffff 180 #define MIPS_XUSEG_START 0x0000000000000000 181 #define MIPS_XUSEG_END 0x0000010000000000 182 #define MIPS_XKSEG_START 0xc000000000000000 183 #define MIPS_XKSEG_END 0xc00000ff80000000 184 #define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000 185 #define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff 186 #define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff) 187 188 #ifdef __mips_n64 189 #define MIPS_DIRECT_MAPPABLE(pa) 1 190 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) 191 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) 192 #define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) 193 #else 194 #define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) 195 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) 196 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) 197 #define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) 198 #endif 199 200 /* CPU dependent mtc0 hazard hook */ 201 #if defined(CPU_CNMIPS) || defined(CPU_RMI) 202 #define COP0_SYNC 203 #elif defined(CPU_SB1) 204 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop 205 #else 206 /* 207 * Pick a reasonable default based on the "typical" spacing described in the 208 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. 209 */ 210 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop 211 #endif 212 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 213 214 /* 215 * The bits in the cause register. 216 * 217 * Bits common to r3000 and r4000: 218 * 219 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 220 * MIPS_CR_COP_ERR Coprocessor error. 221 * MIPS_CR_IP Interrupt pending bits defined below. 222 * (same meaning as in CAUSE register). 223 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 224 * 225 * Differences: 226 * r3k has 4 bits of execption type, r4k has 5 bits. 227 */ 228 #define MIPS_CR_BR_DELAY 0x80000000 229 #define MIPS_CR_COP_ERR 0x30000000 230 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 231 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 232 #define MIPS_CR_IP 0x0000FF00 233 #define MIPS_CR_EXC_CODE_SHIFT 2 234 235 /* 236 * The bits in the status register. All bits are active when set to 1. 237 * 238 * R3000 status register fields: 239 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 240 * MIPS_SR_TS TLB shutdown. 241 * 242 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 243 * 244 * Differences: 245 * r3k has cache control is via frobbing SR register bits, whereas the 246 * r4k cache control is via explicit instructions. 247 * r3k has a 3-entry stack of kernel/user bits, whereas the 248 * r4k has kernel/supervisor/user. 249 */ 250 #define MIPS_SR_COP_USABILITY 0xf0000000 251 #define MIPS_SR_COP_0_BIT 0x10000000 252 #define MIPS_SR_COP_1_BIT 0x20000000 253 #define MIPS_SR_COP_2_BIT 0x40000000 254 255 /* r4k and r3k differences, see below */ 256 257 #define MIPS_SR_MX 0x01000000 /* MIPS64 */ 258 #define MIPS_SR_PX 0x00800000 /* MIPS64 */ 259 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 260 #define MIPS_SR_TS 0x00200000 261 #define MIPS_SR_DE 0x00010000 262 263 #define MIPS_SR_INT_IE 0x00000001 264 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 265 #define MIPS_SR_INT_MASK 0x0000ff00 266 267 /* 268 * The R2000/R3000-specific status register bit definitions. 269 * all bits are active when set to 1. 270 * 271 * MIPS_SR_PARITY_ERR Parity error. 272 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 273 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 274 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 275 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 276 * Interrupt enable bits defined below. 277 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 278 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 279 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 280 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 281 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 282 */ 283 284 #define MIPS1_PARITY_ERR 0x00100000 285 #define MIPS1_CACHE_MISS 0x00080000 286 #define MIPS1_PARITY_ZERO 0x00040000 287 #define MIPS1_SWAP_CACHES 0x00020000 288 #define MIPS1_ISOL_CACHES 0x00010000 289 290 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 291 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 292 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 293 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 294 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 295 296 /* backwards compatibility */ 297 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 298 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 299 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 300 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 301 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 302 303 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 304 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 305 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 306 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 307 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 308 309 /* 310 * R4000 status register bit definitons, 311 * where different from r2000/r3000. 312 */ 313 #define MIPS3_SR_XX 0x80000000 314 #define MIPS3_SR_RP 0x08000000 315 #define MIPS3_SR_FR 0x04000000 316 #define MIPS3_SR_RE 0x02000000 317 318 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 319 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 320 #define MIPS3_SR_SR 0x00100000 321 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 322 #define MIPS3_SR_DIAG_CH 0x00040000 323 #define MIPS3_SR_DIAG_CE 0x00020000 324 #define MIPS3_SR_DIAG_PE 0x00010000 325 #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 326 #define MIPS3_SR_KX 0x00000080 327 #define MIPS3_SR_SX 0x00000040 328 #define MIPS3_SR_UX 0x00000020 329 #define MIPS3_SR_KSU_MASK 0x00000018 330 #define MIPS3_SR_KSU_USER 0x00000010 331 #define MIPS3_SR_KSU_SUPER 0x00000008 332 #define MIPS3_SR_KSU_KERNEL 0x00000000 333 #define MIPS3_SR_ERL 0x00000004 334 #define MIPS3_SR_EXL 0x00000002 335 336 #ifdef MIPS3_5900 337 #undef MIPS_SR_INT_IE 338 #define MIPS_SR_INT_IE 0x00010001 /* XXX */ 339 #endif 340 341 #define MIPS_SR_SOFT_RESET MIPS3_SR_SR 342 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 343 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 344 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 345 #define MIPS_SR_KX MIPS3_SR_KX 346 #define MIPS_SR_SX MIPS3_SR_SX 347 #define MIPS_SR_UX MIPS3_SR_UX 348 349 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 350 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 351 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 352 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 353 #define MIPS_SR_ERL MIPS3_SR_ERL 354 #define MIPS_SR_EXL MIPS3_SR_EXL 355 356 357 /* 358 * The interrupt masks. 359 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 360 */ 361 #define MIPS_INT_MASK 0xff00 362 #define MIPS_INT_MASK_5 0x8000 363 #define MIPS_INT_MASK_4 0x4000 364 #define MIPS_INT_MASK_3 0x2000 365 #define MIPS_INT_MASK_2 0x1000 366 #define MIPS_INT_MASK_1 0x0800 367 #define MIPS_INT_MASK_0 0x0400 368 #define MIPS_HARD_INT_MASK 0xfc00 369 #define MIPS_SOFT_INT_MASK_1 0x0200 370 #define MIPS_SOFT_INT_MASK_0 0x0100 371 372 /* 373 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 374 * choose to enable this interrupt. 375 */ 376 #if defined(MIPS3_ENABLE_CLOCK_INTR) 377 #define MIPS3_INT_MASK MIPS_INT_MASK 378 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 379 #else 380 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 381 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 382 #endif 383 384 /* 385 * The bits in the context register. 386 */ 387 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 388 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 389 390 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 391 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 392 393 /* 394 * Location of MIPS32 exception vectors. Most are multiplexed in 395 * the sense that further decoding is necessary (e.g. reading the 396 * CAUSE register or NMI bits in STATUS). 397 * Most interrupts go via the 398 * The INT vector is dedicated for hardware interrupts; it is 399 * only referenced if the IV bit in CAUSE is set to 1. 400 */ 401 #define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */ 402 #define MIPS_VEC_EJTAG 0xBFC00480 403 #define MIPS_VEC_TLB 0x80000000 404 #define MIPS_VEC_XTLB 0x80000080 405 #define MIPS_VEC_CACHE 0x80000100 406 #define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */ 407 #define MIPS_VEC_INTERRUPT 0x80000200 408 409 /* 410 * The bits in the MIPS3 config register. 411 * 412 * bit 0..5: R/W, Bit 6..31: R/O 413 */ 414 415 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 416 #define MIPS3_CONFIG_K0_MASK 0x00000007 417 418 /* 419 * R/W Update on Store Conditional 420 * 0: Store Conditional uses coherency algorithm specified by TLB 421 * 1: Store Conditional uses cacheable coherent update on write 422 */ 423 #define MIPS3_CONFIG_CU 0x00000008 424 425 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 426 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 427 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 428 (((config) & (bit)) ? 32 : 16) 429 430 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 431 #define MIPS3_CONFIG_DC_SHIFT 6 432 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 433 #define MIPS3_CONFIG_IC_SHIFT 9 434 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 435 436 /* Cache size mode indication: available only on Vr41xx CPUs */ 437 #define MIPS3_CONFIG_CS 0x00001000 438 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 439 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 440 ((base) << (((config) & (mask)) >> (shift))) 441 442 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 443 #define MIPS3_CONFIG_SE 0x00001000 444 445 /* Block ordering: 0: sequential, 1: sub-block */ 446 #define MIPS3_CONFIG_EB 0x00002000 447 448 /* ECC mode - 0: ECC mode, 1: parity mode */ 449 #define MIPS3_CONFIG_EM 0x00004000 450 451 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 452 #define MIPS3_CONFIG_BE 0x00008000 453 454 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 455 #define MIPS3_CONFIG_SM 0x00010000 456 457 /* Secondary Cache - 0: present, 1: not present */ 458 #define MIPS3_CONFIG_SC 0x00020000 459 460 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 461 #define MIPS3_CONFIG_EW_MASK 0x000c0000 462 #define MIPS3_CONFIG_EW_SHIFT 18 463 464 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 465 #define MIPS3_CONFIG_SW 0x00100000 466 467 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 468 #define MIPS3_CONFIG_SS 0x00200000 469 470 /* Secondary Cache line size */ 471 #define MIPS3_CONFIG_SB_MASK 0x00c00000 472 #define MIPS3_CONFIG_SB_SHIFT 22 473 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 474 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 475 476 /* Write back data rate */ 477 #define MIPS3_CONFIG_EP_MASK 0x0f000000 478 #define MIPS3_CONFIG_EP_SHIFT 24 479 480 /* System clock ratio - this value is CPU dependent */ 481 #define MIPS3_CONFIG_EC_MASK 0x70000000 482 #define MIPS3_CONFIG_EC_SHIFT 28 483 484 /* Master-Checker Mode - 1: enabled */ 485 #define MIPS3_CONFIG_CM 0x80000000 486 487 /* 488 * The bits in the MIPS4 config register. 489 */ 490 491 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 492 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 493 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 494 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 495 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 496 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 497 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 498 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 499 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 500 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 501 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 502 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 503 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 504 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 505 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 506 507 #define MIPS4_CONFIG_DC_SHIFT 26 508 #define MIPS4_CONFIG_IC_SHIFT 29 509 510 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 511 ((base) << (((config) & (mask)) >> (shift))) 512 513 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 514 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 515 516 /* 517 * Location of exception vectors. 518 * 519 * Common vectors: reset and UTLB miss. 520 */ 521 #define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 522 #define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 523 524 /* 525 * MIPS-1 general exception vector (everything else) 526 */ 527 #define MIPS1_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000080) 528 529 /* 530 * MIPS-III exception vectors 531 */ 532 #define MIPS3_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 533 #define MIPS3_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 534 #define MIPS3_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 535 536 /* 537 * TX79 (R5900) exception vectors 538 */ 539 #define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 540 #define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 541 542 /* 543 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 544 */ 545 #define MIPS3_INTR_EXC_VEC 0x80000200 546 547 /* 548 * Coprocessor 0 registers: 549 * 550 * v--- width for mips I,III,32,64 551 * (3=32bit, 6=64bit, i=impl dep) 552 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 553 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 554 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 555 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 556 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 557 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 558 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 559 * 7 MIPS_COP_0_INFO ..33 Info registers 560 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 561 * 9 MIPS_COP_0_COUNT .333 Count register. 562 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 563 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 564 * 12 MIPS_COP_0_STATUS 3333 Status register. 565 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 566 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 567 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 568 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 569 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 570 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 571 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 572 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4. 573 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 574 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 575 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 576 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 577 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 578 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 579 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 580 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 581 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 582 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 583 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 584 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 585 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 586 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 587 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 588 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 589 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 590 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 591 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 592 */ 593 594 /* Deal with inclusion from an assembly file. */ 595 #if defined(_LOCORE) || defined(LOCORE) 596 #define _(n) $n 597 #else 598 #define _(n) n 599 #endif 600 601 602 #define MIPS_COP_0_TLB_INDEX _(0) 603 #define MIPS_COP_0_TLB_RANDOM _(1) 604 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 605 606 #define MIPS_COP_0_TLB_CONTEXT _(4) 607 /* $5 and $6 new with MIPS-III */ 608 #define MIPS_COP_0_BAD_VADDR _(8) 609 #define MIPS_COP_0_TLB_HI _(10) 610 #define MIPS_COP_0_STATUS _(12) 611 #define MIPS_COP_0_CAUSE _(13) 612 #define MIPS_COP_0_EXC_PC _(14) 613 #define MIPS_COP_0_PRID _(15) 614 615 /* MIPS-III */ 616 #define MIPS_COP_0_TLB_LO0 _(2) 617 #define MIPS_COP_0_TLB_LO1 _(3) 618 619 #define MIPS_COP_0_TLB_PG_MASK _(5) 620 #define MIPS_COP_0_TLB_WIRED _(6) 621 622 #define MIPS_COP_0_COUNT _(9) 623 #define MIPS_COP_0_COMPARE _(11) 624 625 #define MIPS_COP_0_CONFIG _(16) 626 #define MIPS_COP_0_LLADDR _(17) 627 #define MIPS_COP_0_WATCH_LO _(18) 628 #define MIPS_COP_0_WATCH_HI _(19) 629 #define MIPS_COP_0_TLB_XCONTEXT _(20) 630 #define MIPS_COP_0_ECC _(26) 631 #define MIPS_COP_0_CACHE_ERR _(27) 632 #define MIPS_COP_0_TAG_LO _(28) 633 #define MIPS_COP_0_TAG_HI _(29) 634 #define MIPS_COP_0_ERROR_PC _(30) 635 636 /* MIPS32/64 */ 637 #define MIPS_COP_0_INFO _(7) 638 #define MIPS_COP_0_DEBUG _(23) 639 #define MIPS_COP_0_DEPC _(24) 640 #define MIPS_COP_0_PERFCNT _(25) 641 #define MIPS_COP_0_DATA_LO _(28) 642 #define MIPS_COP_0_DATA_HI _(29) 643 #define MIPS_COP_0_DESAVE _(31) 644 645 /* MIPS32 Config register definitions */ 646 #define MIPS_MMU_NONE 0x00 /* No MMU present */ 647 #define MIPS_MMU_TLB 0x01 /* Standard TLB */ 648 #define MIPS_MMU_BAT 0x02 /* Standard BAT */ 649 #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ 650 651 #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ 652 #define MIPS_CONFIG0_MT_SHIFT 7 653 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ 654 #define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ 655 656 #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ 657 #define MIPS_CONFIG1_TLBSZ_SHIFT 25 658 #define MIPS_MAX_TLB_ENTRIES 128 659 660 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ 661 #define MIPS_CONFIG1_IS_SHIFT 22 662 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ 663 #define MIPS_CONFIG1_IL_SHIFT 19 664 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ 665 #define MIPS_CONFIG1_IA_SHIFT 16 666 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ 667 #define MIPS_CONFIG1_DS_SHIFT 13 668 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ 669 #define MIPS_CONFIG1_DL_SHIFT 10 670 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ 671 #define MIPS_CONFIG1_DA_SHIFT 7 672 #define MIPS_CONFIG1_LOWBITS 0x0000007F 673 #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 674 #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 675 #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 676 #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 677 #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 678 #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 679 #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 680 681 #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 682 #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 683 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 684 685 /* 686 * Values for the code field in a break instruction. 687 */ 688 #define MIPS_BREAK_INSTR 0x0000000d 689 #define MIPS_BREAK_VAL_MASK 0x03ff0000 690 #define MIPS_BREAK_VAL_SHIFT 16 691 #define MIPS_BREAK_KDB_VAL 512 692 #define MIPS_BREAK_SSTEP_VAL 513 693 #define MIPS_BREAK_BRKPT_VAL 514 694 #define MIPS_BREAK_SOVER_VAL 515 695 #define MIPS_BREAK_DDB_VAL 516 696 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 697 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 698 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 699 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 700 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 701 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 702 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 703 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 704 #define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 705 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 706 707 /* 708 * Mininum and maximum cache sizes. 709 */ 710 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 711 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 712 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 713 714 /* 715 * The floating point version and status registers. 716 */ 717 #define MIPS_FPU_ID $0 718 #define MIPS_FPU_CSR $31 719 720 /* 721 * The floating point coprocessor status register bits. 722 */ 723 #define MIPS_FPU_ROUNDING_BITS 0x00000003 724 #define MIPS_FPU_ROUND_RN 0x00000000 725 #define MIPS_FPU_ROUND_RZ 0x00000001 726 #define MIPS_FPU_ROUND_RP 0x00000002 727 #define MIPS_FPU_ROUND_RM 0x00000003 728 #define MIPS_FPU_STICKY_BITS 0x0000007c 729 #define MIPS_FPU_STICKY_INEXACT 0x00000004 730 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 731 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 732 #define MIPS_FPU_STICKY_DIV0 0x00000020 733 #define MIPS_FPU_STICKY_INVALID 0x00000040 734 #define MIPS_FPU_ENABLE_BITS 0x00000f80 735 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 736 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 737 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 738 #define MIPS_FPU_ENABLE_DIV0 0x00000400 739 #define MIPS_FPU_ENABLE_INVALID 0x00000800 740 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 741 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 742 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 743 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 744 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 745 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 746 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 747 #define MIPS_FPU_COND_BIT 0x00800000 748 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 749 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 750 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 751 752 753 /* 754 * Constants to determine if have a floating point instruction. 755 */ 756 #define MIPS_OPCODE_SHIFT 26 757 #define MIPS_OPCODE_C1 0x11 758 759 760 /* 761 * The low part of the TLB entry. 762 */ 763 #define MIPS1_TLB_PFN 0xfffff000 764 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 765 #define MIPS1_TLB_DIRTY_BIT 0x00000400 766 #define MIPS1_TLB_VALID_BIT 0x00000200 767 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 768 769 #define MIPS3_TLB_PFN 0x3fffffc0 770 #define MIPS3_TLB_ATTR_MASK 0x00000038 771 #define MIPS3_TLB_ATTR_SHIFT 3 772 #define MIPS3_TLB_DIRTY_BIT 0x00000004 773 #define MIPS3_TLB_VALID_BIT 0x00000002 774 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 775 776 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 777 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 778 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 779 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 780 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 781 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 782 783 /* 784 * MIPS3_TLB_ATTR values - coherency algorithm: 785 * 0: cacheable, noncoherent, write-through, no write allocate 786 * 1: cacheable, noncoherent, write-through, write allocate 787 * 2: uncached 788 * 3: cacheable, noncoherent, write-back (noncoherent) 789 * 4: cacheable, coherent, write-back, exclusive (exclusive) 790 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 791 * 6: cacheable, coherent, write-back, update on write (update) 792 * 7: uncached, accelerated (gather STORE operations) 793 */ 794 #define MIPS3_TLB_ATTR_WT 0 /* IDT */ 795 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 796 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 797 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 798 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 799 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 800 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 801 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 802 803 804 /* 805 * The high part of the TLB entry. 806 */ 807 #define MIPS1_TLB_VPN 0xfffff000 808 #define MIPS1_TLB_PID 0x00000fc0 809 #define MIPS1_TLB_PID_SHIFT 6 810 811 #define MIPS3_TLB_VPN2 0xffffe000 812 #define MIPS3_TLB_ASID 0x000000ff 813 814 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 815 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 816 #define MIPS3_TLB_PID MIPS3_TLB_ASID 817 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 818 819 /* 820 * r3000: shift count to put the index in the right spot. 821 */ 822 #define MIPS1_TLB_INDEX_SHIFT 8 823 824 /* 825 * The first TLB that write random hits. 826 */ 827 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 828 #define MIPS3_TLB_WIRED_UPAGES 1 829 830 /* 831 * The number of process id entries. 832 */ 833 #define MIPS1_TLB_NUM_PIDS 64 834 #define MIPS3_TLB_NUM_ASIDS 256 835 836 /* 837 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 838 */ 839 840 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 841 842 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 843 && defined(MIPS1) /* XXX simonb must be neater! */ 844 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 845 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 846 #endif 847 848 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 849 && !defined(MIPS1) /* XXX simonb must be neater! */ 850 #define MIPS_TLB_PID_SHIFT 0 851 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 852 #endif 853 854 855 #if !defined(MIPS_TLB_PID_SHIFT) 856 #define MIPS_TLB_PID_SHIFT \ 857 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 858 859 #define MIPS_TLB_NUM_PIDS \ 860 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 861 #endif 862 863 /* 864 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 865 */ 866 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 867 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 868 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 869 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 870 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 871 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 872 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 873 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 874 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 875 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 876 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 877 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 878 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 879 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 880 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 881 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 882 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 883 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 884 #define MIPS_R4650 0x22 /* QED R4650 ISA III */ 885 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 886 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 887 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 888 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 889 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 890 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 891 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 892 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 893 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 894 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 895 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 896 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 897 898 /* 899 * CPU revision IDs for some prehistoric processors. 900 */ 901 902 /* For MIPS_R3000 */ 903 #define MIPS_REV_R3000 0x20 904 #define MIPS_REV_R3000A 0x30 905 906 /* For MIPS_TX3900 */ 907 #define MIPS_REV_TX3912 0x10 908 #define MIPS_REV_TX3922 0x30 909 #define MIPS_REV_TX3927 0x40 910 911 /* For MIPS_R4000 */ 912 #define MIPS_REV_R4000_A 0x00 913 #define MIPS_REV_R4000_B 0x22 914 #define MIPS_REV_R4000_C 0x30 915 #define MIPS_REV_R4400_A 0x40 916 #define MIPS_REV_R4400_B 0x50 917 #define MIPS_REV_R4400_C 0x60 918 919 /* For MIPS_TX4900 */ 920 #define MIPS_REV_TX4927 0x22 921 922 /* 923 * CPU processor revision IDs for company ID == 1 (MIPS) 924 */ 925 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 926 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 927 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 928 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 929 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 930 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 931 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 932 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 933 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 934 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 935 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 936 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 937 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 938 #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 939 #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 940 #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 941 #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 942 943 /* 944 * AMD (company ID 3) use the processor ID field to donote the CPU core 945 * revision and the company options field do donate the SOC chip type. 946 */ 947 948 /* CPU processor revision IDs */ 949 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 950 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 951 952 /* CPU company options IDs */ 953 #define MIPS_AU1000 0x00 954 #define MIPS_AU1500 0x01 955 #define MIPS_AU1100 0x02 956 #define MIPS_AU1550 0x03 957 958 /* 959 * CPU processor revision IDs for company ID == 4 (Broadcom) 960 */ 961 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 962 963 /* 964 * CPU processor revision IDs for company ID == 5 (SandCraft) 965 */ 966 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 967 968 /* 969 * FPU processor revision ID 970 */ 971 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 972 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 973 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 974 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 975 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 976 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 977 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 978 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 979 980 #ifdef ENABLE_MIPS_TX3900 981 #include <mips/r3900regs.h> 982 #endif 983 #ifdef MIPS3_5900 984 #include <mips/r5900regs.h> 985 #endif 986 #ifdef MIPS64_SB1 987 #include <mips/sb1regs.h> 988 #endif 989 990 #endif /* _MIPS_CPUREGS_H_ */ 991