Searched refs:MFLO (Results 1 – 8 of 8) sorted by relevance
| /freebsd-9-stable/contrib/gcc/config/mips/ |
| D | 4k.md | 90 ;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
107 ;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
115 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
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| D | 5k.md | 89 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
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| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 98 Opc = Mips::MFLO, SrcReg = 0; in copyPhysReg()
273 expandPseudoMFHiLo(MBB, MI, Mips::MFLO); in expandPostRAPseudo()
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| D | MipsISelLowering.h | 74 MFLO, enumerator
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| D | MipsSEISelLowering.cpp | 346 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
418 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); in selectMSUB()
1164 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); in lowerMulDiv()
1185 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); in extractLOHI()
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| D | MipsInstrInfo.td | 89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
1062 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
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| D | Mips16InstrInfo.td | 868 // Format: MFLO rx MIPS16e
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| D | MipsISelLowering.cpp | 131 case MipsISD::MFLO: return "MipsISD::MFLO"; in getTargetNodeName()
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