| /freebsd-9-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 3829 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, in expandExp()
3850 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in expandExp()
3854 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in expandExp()
3866 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in expandExp()
3870 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in expandExp()
3873 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in expandExp()
3888 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in expandExp()
3892 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in expandExp()
3895 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in expandExp()
3898 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in expandExp()
[all …]
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| D | DAGCombiner.cpp | 469 case ISD::FMUL: in isNegatibleForFree()
537 case ISD::FMUL: in GetNegatedExpression()
1169 case ISD::FMUL: return visitFMUL(N); in visit()
6041 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && in visitFADD()
6043 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
6052 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, in visitFADD()
6061 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, in visitFADD()
6072 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, in visitFADD()
6083 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, in visitFADD()
6088 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
[all …]
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| D | LegalizeVectorOps.cpp | 202 case ISD::FMUL: in LegalizeOp()
734 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
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| D | SelectionDAGDumper.cpp | 176 case ISD::FMUL: return "fmul"; in getOperationName()
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| D | SelectionDAGBuilder.h | 696 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); } in visitFMul()
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| D | LegalizeFloatTypes.cpp | 81 case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break; in SoftenFloatResult()
826 case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 103 case ISD::FMUL: in ScalarizeVectorResult()
569 case ISD::FMUL: in SplitVectorResult()
1525 case ISD::FMUL: in WidenVectorResult()
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| D | FastISel.cpp | 993 return SelectBinaryOp(I, ISD::FMUL); in SelectOperator()
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| D | SelectionDAG.cpp | 2952 case ISD::FMUL: in getNode()
2970 } else if (Opcode == ISD::FMUL) { in getNode()
3218 case ISD::FMUL: in getNode()
3300 case ISD::FMUL: in getNode()
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| /freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 222 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
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| D | SelectionDAG.h | 1003 case ISD::FMUL:
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| /freebsd-9-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 188 setOperationAction(ISD::FMUL, VT, Expand); in AMDGPUTargetLowering()
422 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, in LowerIntrinsicLRP()
425 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), in LowerIntrinsicLRP()
725 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi, in LowerUINT_TO_FP()
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| D | AMDILISelLowering.cpp | 174 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); in InitAMDILLowering()
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| D | R600ISelLowering.cpp | 791 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg, in LowerTrig()
811 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal, in LowerTrig()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 230 setOperationAction(ISD::FMUL, Ty, Legal); in addMSAFloatType()
1732 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1744 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1750 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, in lowerINTRINSIC_WO_CHAIN()
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| D | MipsInstrFPU.td | 420 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6783 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est); in DAGCombineFastRecip()
6789 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst); in DAGCombineFastRecip()
6846 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op); in DAGCombineFastRecipFSQRT()
6854 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est); in DAGCombineFastRecipFSQRT()
6857 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst); in DAGCombineFastRecipFSQRT()
6863 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst); in DAGCombineFastRecipFSQRT()
7017 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), in PerformDAGCombine()
7030 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), in PerformDAGCombine()
7044 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), in PerformDAGCombine()
7052 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), in PerformDAGCombine()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1596 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1621 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
2823 case ISD::FMUL: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd-9-stable/contrib/binutils/opcodes/ |
| D | ChangeLog-0001 | 1873 FMUL instruction.
1874 (reg_fmul_r): New. Extract source register from FMUL instruction.
1879 (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
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| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 479 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); in ARMTargetLowering()
5786 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); in LowerSDIV_v4i8()
5817 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerSDIV_v4i16()
5822 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
5922 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
5926 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
5931 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
9612 Op.getOpcode() != ISD::FMUL) in PerformVCVTCombine()
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| D | ARMFastISel.cpp | 1893 case ISD::FMUL: in SelectBinaryFPOp()
2923 return SelectBinaryFPOp(I, ISD::FMUL); in TargetSelectInstruction()
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| /freebsd-9-stable/contrib/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1259 case FMul: return ISD::FMUL; in InstructionOpcodeToISD()
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| /freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1261 setOperationAction(ISD::FMUL, MVT::f64, Expand); in HexagonTargetLowering()
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| /freebsd-9-stable/contrib/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 368 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
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| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 231 setOperationAction(ISD::FMUL, MVT::f128, Custom); in AArch64TargetLowering()
2868 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128); in LowerOperation()
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