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38 ***********************license end**************************************/
39
40
41
42
43
44
45
46 /**
47 * @file
48 *
49 * Interface to the Mips interrupts.
50 *
51 * <hr>$Revision: 49448 $<hr>
52 */
53 #ifndef __CVMX_INTERRUPT_H__
54 #define __CVMX_INTERRUPT_H__
55
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59
60 /**
61 * Enumeration of Interrupt numbers
62 */
63 typedef enum
64 {
65 /* 0 - 7 represent the 8 MIPS standard interrupt sources */
66 CVMX_IRQ_SW0 = 0,
67 CVMX_IRQ_SW1 = 1,
68 CVMX_IRQ_CIU0 = 2,
69 CVMX_IRQ_CIU1 = 3,
70 CVMX_IRQ_4 = 4,
71 CVMX_IRQ_5 = 5,
72 CVMX_IRQ_6 = 6,
73 CVMX_IRQ_7 = 7,
74
75 /* 8 - 71 represent the sources in CIU_INTX_EN0 */
76 CVMX_IRQ_WORKQ0 = 8,
77 CVMX_IRQ_WORKQ1 = 9,
78 CVMX_IRQ_WORKQ2 = 10,
79 CVMX_IRQ_WORKQ3 = 11,
80 CVMX_IRQ_WORKQ4 = 12,
81 CVMX_IRQ_WORKQ5 = 13,
82 CVMX_IRQ_WORKQ6 = 14,
83 CVMX_IRQ_WORKQ7 = 15,
84 CVMX_IRQ_WORKQ8 = 16,
85 CVMX_IRQ_WORKQ9 = 17,
86 CVMX_IRQ_WORKQ10 = 18,
87 CVMX_IRQ_WORKQ11 = 19,
88 CVMX_IRQ_WORKQ12 = 20,
89 CVMX_IRQ_WORKQ13 = 21,
90 CVMX_IRQ_WORKQ14 = 22,
91 CVMX_IRQ_WORKQ15 = 23,
92 CVMX_IRQ_GPIO0 = 24,
93 CVMX_IRQ_GPIO1 = 25,
94 CVMX_IRQ_GPIO2 = 26,
95 CVMX_IRQ_GPIO3 = 27,
96 CVMX_IRQ_GPIO4 = 28,
97 CVMX_IRQ_GPIO5 = 29,
98 CVMX_IRQ_GPIO6 = 30,
99 CVMX_IRQ_GPIO7 = 31,
100 CVMX_IRQ_GPIO8 = 32,
101 CVMX_IRQ_GPIO9 = 33,
102 CVMX_IRQ_GPIO10 = 34,
103 CVMX_IRQ_GPIO11 = 35,
104 CVMX_IRQ_GPIO12 = 36,
105 CVMX_IRQ_GPIO13 = 37,
106 CVMX_IRQ_GPIO14 = 38,
107 CVMX_IRQ_GPIO15 = 39,
108 CVMX_IRQ_MBOX0 = 40,
109 CVMX_IRQ_MBOX1 = 41,
110 CVMX_IRQ_UART0 = 42,
111 CVMX_IRQ_UART1 = 43,
112 CVMX_IRQ_PCI_INT0 = 44,
113 CVMX_IRQ_PCI_INT1 = 45,
114 CVMX_IRQ_PCI_INT2 = 46,
115 CVMX_IRQ_PCI_INT3 = 47,
116 CVMX_IRQ_PCI_MSI0 = 48,
117 CVMX_IRQ_PCI_MSI1 = 49,
118 CVMX_IRQ_PCI_MSI2 = 50,
119 CVMX_IRQ_PCI_MSI3 = 51,
120 CVMX_IRQ_RESERVED44 = 52,
121 CVMX_IRQ_TWSI = 53,
122 CVMX_IRQ_RML = 54,
123 CVMX_IRQ_TRACE = 55,
124 CVMX_IRQ_GMX_DRP0 = 56,
125 CVMX_IRQ_GMX_DRP1 = 57, /* Doesn't apply on CN52XX or CN63XX */
126 CVMX_IRQ_IPD_DRP = 58,
127 CVMX_IRQ_KEY_ZERO = 59, /* Doesn't apply on CN52XX or CN63XX */
128 CVMX_IRQ_TIMER0 = 60,
129 CVMX_IRQ_TIMER1 = 61,
130 CVMX_IRQ_TIMER2 = 62,
131 CVMX_IRQ_TIMER3 = 63,
132 CVMX_IRQ_USB0 = 64, /* Doesn't apply on CN38XX or CN58XX */
133 CVMX_IRQ_PCM = 65, /* Doesn't apply on CN52XX or CN63XX */
134 CVMX_IRQ_MPI = 66, /* Doesn't apply on CN52XX or CN63XX */
135 CVMX_IRQ_TWSI2 = 67, /* Added in CN56XX */
136 CVMX_IRQ_POWIQ = 68, /* Added in CN56XX */
137 CVMX_IRQ_IPDPPTHR = 69, /* Added in CN56XX */
138 CVMX_IRQ_MII = 70, /* Added in CN56XX */
139 CVMX_IRQ_BOOTDMA = 71, /* Added in CN56XX */
140
141 /* 72 - 135 represent the sources in CIU_INTX_EN1 */
142 CVMX_IRQ_WDOG0 = 72,
143 CVMX_IRQ_WDOG1 = 73,
144 CVMX_IRQ_WDOG2 = 74,
145 CVMX_IRQ_WDOG3 = 75,
146 CVMX_IRQ_WDOG4 = 76,
147 CVMX_IRQ_WDOG5 = 77,
148 CVMX_IRQ_WDOG6 = 78,
149 CVMX_IRQ_WDOG7 = 79,
150 CVMX_IRQ_WDOG8 = 80,
151 CVMX_IRQ_WDOG9 = 81,
152 CVMX_IRQ_WDOG10= 82,
153 CVMX_IRQ_WDOG11= 83,
154 CVMX_IRQ_WDOG12= 84,
155 CVMX_IRQ_WDOG13= 85,
156 CVMX_IRQ_WDOG14= 86,
157 CVMX_IRQ_WDOG15= 87,
158 CVMX_IRQ_UART2 = 88, /* Added in CN52XX */
159 CVMX_IRQ_USB1 = 89, /* Added in CN52XX */
160 CVMX_IRQ_MII1 = 90, /* Added in CN52XX */
161 CVMX_IRQ_NAND = 91, /* Added in CN52XX */
162 CVMX_IRQ_MIO = 92, /* Added in CN63XX */
163 CVMX_IRQ_IOB = 93, /* Added in CN63XX */
164 CVMX_IRQ_FPA = 94, /* Added in CN63XX */
165 CVMX_IRQ_POW = 95, /* Added in CN63XX */
166 CVMX_IRQ_L2C = 96, /* Added in CN63XX */
167 CVMX_IRQ_IPD = 97, /* Added in CN63XX */
168 CVMX_IRQ_PIP = 98, /* Added in CN63XX */
169 CVMX_IRQ_PKO = 99, /* Added in CN63XX */
170 CVMX_IRQ_ZIP = 100, /* Added in CN63XX */
171 CVMX_IRQ_TIM = 101, /* Added in CN63XX */
172 CVMX_IRQ_RAD = 102, /* Added in CN63XX */
173 CVMX_IRQ_KEY = 103, /* Added in CN63XX */
174 CVMX_IRQ_DFA = 104, /* Added in CN63XX */
175 CVMX_IRQ_USB = 105, /* Added in CN63XX */
176 CVMX_IRQ_SLI = 106, /* Added in CN63XX */
177 CVMX_IRQ_DPI = 107, /* Added in CN63XX */
178 CVMX_IRQ_AGX0 = 108, /* Added in CN63XX */
179 /* 109 - 117 are reserved */
180 CVMX_IRQ_AGL = 118, /* Added in CN63XX */
181 CVMX_IRQ_PTP = 119, /* Added in CN63XX */
182 CVMX_IRQ_PEM0 = 120, /* Added in CN63XX */
183 CVMX_IRQ_PEM1 = 121, /* Added in CN63XX */
184 CVMX_IRQ_SRIO0 = 122, /* Added in CN63XX */
185 CVMX_IRQ_SRIO1 = 123, /* Added in CN63XX */
186 CVMX_IRQ_LMC0 = 124, /* Added in CN63XX */
187 /* Interrupts 125 - 127 are reserved */
188 CVMX_IRQ_DFM = 128, /* Added in CN63XX */
189 /* Interrupts 129 - 135 are reserved */
190 } cvmx_irq_t;
191
192 /**
193 * Function prototype for the exception handler
194 */
195 typedef void (*cvmx_interrupt_exception_t)(uint64_t registers[32]);
196
197 /**
198 * Function prototype for interrupt handlers
199 */
200 typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t registers[32], void *user_arg);
201
202 /**
203 * Register an interrupt handler for the specified interrupt number.
204 *
205 * @param irq_number Interrupt number to register for (0-135)
206 * @param func Function to call on interrupt.
207 * @param user_arg User data to pass to the interrupt handler
208 */
209 void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg);
210
211 /**
212 * Set the exception handler for all non interrupt sources.
213 *
214 * @param handler New exception handler
215 * @return Old exception handler
216 */
217 cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler);
218
219 /**
220 * Masks a given interrupt number.
221 * EN0 sources are masked on IP2
222 * EN1 sources are masked on IP3
223 *
224 * @param irq_number interrupt number to mask (0-135)
225 */
cvmx_interrupt_mask_irq(int irq_number)226 static inline void cvmx_interrupt_mask_irq(int irq_number)
227 {
228 if (irq_number<8)
229 {
230 uint32_t mask;
231 asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
232 mask &= ~(1<< (8 + irq_number));
233 asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
234 }
235 else if (irq_number < 8 + 64)
236 {
237 int ciu_bit = (irq_number - 8) & 63;
238 int ciu_offset = cvmx_get_core_num() * 2;
239 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
240 mask &= ~(1ull << ciu_bit);
241 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
242 }
243 else
244 {
245 int ciu_bit = (irq_number - 8) & 63;
246 int ciu_offset = cvmx_get_core_num() * 2 + 1;
247 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
248 mask &= ~(1ull << ciu_bit);
249 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
250 }
251 }
252
253
254 /**
255 * Unmasks a given interrupt number
256 * EN0 sources are unmasked on IP2
257 * EN1 sources are unmasked on IP3
258 *
259 * @param irq_number interrupt number to unmask (0-135)
260 */
cvmx_interrupt_unmask_irq(int irq_number)261 static inline void cvmx_interrupt_unmask_irq(int irq_number)
262 {
263 if (irq_number<8)
264 {
265 uint32_t mask;
266 asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
267 mask |= (1<< (8 + irq_number));
268 asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
269 }
270 else if (irq_number < 8 + 64)
271 {
272 int ciu_bit = (irq_number - 8) & 63;
273 int ciu_offset = cvmx_get_core_num() * 2;
274 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
275 mask |= (1ull << ciu_bit);
276 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
277 }
278 else
279 {
280 int ciu_bit = (irq_number - 8) & 63;
281 int ciu_offset = cvmx_get_core_num() * 2 + 1;
282 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
283 mask |= (1ull << ciu_bit);
284 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
285 }
286 }
287
288
289 /* Disable interrupts by clearing bit 0 of the COP0 status register,
290 ** and return the previous contents of the status register.
291 ** Note: this is only used to track interrupt status. */
cvmx_interrupt_disable_save(void)292 static inline uint32_t cvmx_interrupt_disable_save(void)
293 {
294 uint32_t flags;
295 asm volatile (
296 "DI %[flags]\n"
297 : [flags]"=r" (flags));
298 return(flags);
299 }
300
301 /* Restore the contents of the cop0 status register. Used with
302 ** cvmx_interrupt_disable_save to allow recursive interrupt disabling */
cvmx_interrupt_restore(uint32_t flags)303 static inline void cvmx_interrupt_restore(uint32_t flags)
304 {
305 /* If flags value indicates interrupts should be enabled, then enable them */
306 if (flags & 1)
307 {
308 asm volatile (
309 "EI \n"
310 ::);
311 }
312 }
313
314 #define cvmx_local_irq_save(x) ({x = cvmx_interrupt_disable_save();})
315 #define cvmx_local_irq_restore(x) cvmx_interrupt_restore(x)
316
317 /**
318 * Utility function to do interrupt safe printf
319 */
320 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
321 #define cvmx_safe_printf printk
322 #elif defined(CVMX_BUILD_FOR_LINUX_USER)
323 #define cvmx_safe_printf printf
324 #else
325 extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));
326 #endif
327
328 #define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
329
330 #ifdef __cplusplus
331 }
332 #endif
333
334 #endif
335