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39
40
41 /**
42 * cvmx-iob-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon iob.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_IOB_TYPEDEFS_H__
53 #define __CVMX_IOB_TYPEDEFS_H__
54
55 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
56 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
57 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
58 #define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
CVMX_IOB_DWB_PRI_CNT_FUNC(void)59 static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
60 {
61 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
62 cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
63 return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
64 }
65 #else
66 #define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
67 #endif
68 #define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
69 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
70 #define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
CVMX_IOB_I2C_PRI_CNT_FUNC(void)71 static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
72 {
73 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
74 cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
75 return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
76 }
77 #else
78 #define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
79 #endif
80 #define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
81 #define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
82 #define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
83 #define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
84 #define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
85 #define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
86 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
87 #define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)88 static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
89 {
90 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
91 cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
92 return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
93 }
94 #else
95 #define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
96 #endif
97 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98 #define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)99 static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
100 {
101 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
102 cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
103 return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
104 }
105 #else
106 #define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
107 #endif
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
109 #define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)110 static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
111 {
112 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
113 cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
114 return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
115 }
116 #else
117 #define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
118 #endif
119 #define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
120 #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
121 #define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
122 #define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
124 #define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)125 static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
126 {
127 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
128 cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
129 return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
130 }
131 #else
132 #define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
133 #endif
134 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
135 #define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)136 static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
137 {
138 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
139 cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
140 return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
141 }
142 #else
143 #define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
144 #endif
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
146 #define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)147 static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
148 {
149 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
150 cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
151 return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
152 }
153 #else
154 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
155 #endif
156 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
157 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
158 #define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
CVMX_IOB_TO_CMB_CREDITS_FUNC(void)159 static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
160 {
161 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
162 cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
163 return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
164 }
165 #else
166 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
167 #endif
168
169 /**
170 * cvmx_iob_bist_status
171 *
172 * IOB_BIST_STATUS = BIST Status of IOB Memories
173 *
174 * The result of the BIST run on the IOB memories.
175 */
176 union cvmx_iob_bist_status
177 {
178 uint64_t u64;
179 struct cvmx_iob_bist_status_s
180 {
181 #if __BYTE_ORDER == __BIG_ENDIAN
182 uint64_t reserved_23_63 : 41;
183 uint64_t xmdfif : 1; /**< xmdfif_bist_status */
184 uint64_t xmcfif : 1; /**< xmcfif_bist_status */
185 uint64_t iorfif : 1; /**< iorfif_bist_status */
186 uint64_t rsdfif : 1; /**< rsdfif_bist_status */
187 uint64_t iocfif : 1; /**< iocfif_bist_status */
188 uint64_t icnrcb : 1; /**< icnr_cb_reg_fifo_bist_status */
189 uint64_t icr0 : 1; /**< icr_bist_req_fifo0_status */
190 uint64_t icr1 : 1; /**< icr_bist_req_fifo1_status */
191 uint64_t icnr1 : 1; /**< Reserved */
192 uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */
193 uint64_t ibdr0 : 1; /**< ibdr_bist_req_fifo0_status */
194 uint64_t ibdr1 : 1; /**< ibdr_bist_req_fifo1_status */
195 uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */
196 uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */
197 uint64_t icnrt : 1; /**< icnr_tag_cb_reg_fifo_bist_status */
198 uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */
199 uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */
200 uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */
201 uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */
202 uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */
203 uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */
204 uint64_t ibd : 1; /**< ibd_bist_mem0_status */
205 uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */
206 #else
207 uint64_t icd : 1;
208 uint64_t ibd : 1;
209 uint64_t icrp1 : 1;
210 uint64_t icrp0 : 1;
211 uint64_t icrn1 : 1;
212 uint64_t icrn0 : 1;
213 uint64_t ibrq1 : 1;
214 uint64_t ibrq0 : 1;
215 uint64_t icnrt : 1;
216 uint64_t ibr1 : 1;
217 uint64_t ibr0 : 1;
218 uint64_t ibdr1 : 1;
219 uint64_t ibdr0 : 1;
220 uint64_t icnr0 : 1;
221 uint64_t icnr1 : 1;
222 uint64_t icr1 : 1;
223 uint64_t icr0 : 1;
224 uint64_t icnrcb : 1;
225 uint64_t iocfif : 1;
226 uint64_t rsdfif : 1;
227 uint64_t iorfif : 1;
228 uint64_t xmcfif : 1;
229 uint64_t xmdfif : 1;
230 uint64_t reserved_23_63 : 41;
231 #endif
232 } s;
233 struct cvmx_iob_bist_status_cn30xx
234 {
235 #if __BYTE_ORDER == __BIG_ENDIAN
236 uint64_t reserved_18_63 : 46;
237 uint64_t icnrcb : 1; /**< Reserved */
238 uint64_t icr0 : 1; /**< Reserved */
239 uint64_t icr1 : 1; /**< Reserved */
240 uint64_t icnr1 : 1; /**< Reserved */
241 uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */
242 uint64_t ibdr0 : 1; /**< ibdr_bist_req_fifo0_status */
243 uint64_t ibdr1 : 1; /**< ibdr_bist_req_fifo1_status */
244 uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */
245 uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */
246 uint64_t icnrt : 1; /**< Reserved */
247 uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */
248 uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */
249 uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */
250 uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */
251 uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */
252 uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */
253 uint64_t ibd : 1; /**< ibd_bist_mem0_status */
254 uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */
255 #else
256 uint64_t icd : 1;
257 uint64_t ibd : 1;
258 uint64_t icrp1 : 1;
259 uint64_t icrp0 : 1;
260 uint64_t icrn1 : 1;
261 uint64_t icrn0 : 1;
262 uint64_t ibrq1 : 1;
263 uint64_t ibrq0 : 1;
264 uint64_t icnrt : 1;
265 uint64_t ibr1 : 1;
266 uint64_t ibr0 : 1;
267 uint64_t ibdr1 : 1;
268 uint64_t ibdr0 : 1;
269 uint64_t icnr0 : 1;
270 uint64_t icnr1 : 1;
271 uint64_t icr1 : 1;
272 uint64_t icr0 : 1;
273 uint64_t icnrcb : 1;
274 uint64_t reserved_18_63 : 46;
275 #endif
276 } cn30xx;
277 struct cvmx_iob_bist_status_cn30xx cn31xx;
278 struct cvmx_iob_bist_status_cn30xx cn38xx;
279 struct cvmx_iob_bist_status_cn30xx cn38xxp2;
280 struct cvmx_iob_bist_status_cn30xx cn50xx;
281 struct cvmx_iob_bist_status_cn30xx cn52xx;
282 struct cvmx_iob_bist_status_cn30xx cn52xxp1;
283 struct cvmx_iob_bist_status_cn30xx cn56xx;
284 struct cvmx_iob_bist_status_cn30xx cn56xxp1;
285 struct cvmx_iob_bist_status_cn30xx cn58xx;
286 struct cvmx_iob_bist_status_cn30xx cn58xxp1;
287 struct cvmx_iob_bist_status_s cn63xx;
288 struct cvmx_iob_bist_status_s cn63xxp1;
289 };
290 typedef union cvmx_iob_bist_status cvmx_iob_bist_status_t;
291
292 /**
293 * cvmx_iob_ctl_status
294 *
295 * IOB Control Status = IOB Control and Status Register
296 *
297 * Provides control for IOB functions.
298 */
299 union cvmx_iob_ctl_status
300 {
301 uint64_t u64;
302 struct cvmx_iob_ctl_status_s
303 {
304 #if __BYTE_ORDER == __BIG_ENDIAN
305 uint64_t reserved_10_63 : 54;
306 uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */
307 uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next
308 transaction that could arbitrate for the XMB. */
309 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
310 matchers. PASS2 FIELD. */
311 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
312 matchers. PASS2 FIELD. */
313 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
314 '0' is for big-endian and '1' is for little-endian. */
315 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
316 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
317 big-endian and '1' is for little-endian. */
318 #else
319 uint64_t fau_end : 1;
320 uint64_t dwb_enb : 1;
321 uint64_t pko_enb : 1;
322 uint64_t inb_mat : 1;
323 uint64_t outb_mat : 1;
324 uint64_t rr_mode : 1;
325 uint64_t xmc_per : 4;
326 uint64_t reserved_10_63 : 54;
327 #endif
328 } s;
329 struct cvmx_iob_ctl_status_cn30xx
330 {
331 #if __BYTE_ORDER == __BIG_ENDIAN
332 uint64_t reserved_5_63 : 59;
333 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
334 matchers. */
335 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
336 matchers. */
337 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
338 '0' is for big-endian and '1' is for little-endian. */
339 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
340 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
341 big-endian and '1' is for little-endian. */
342 #else
343 uint64_t fau_end : 1;
344 uint64_t dwb_enb : 1;
345 uint64_t pko_enb : 1;
346 uint64_t inb_mat : 1;
347 uint64_t outb_mat : 1;
348 uint64_t reserved_5_63 : 59;
349 #endif
350 } cn30xx;
351 struct cvmx_iob_ctl_status_cn30xx cn31xx;
352 struct cvmx_iob_ctl_status_cn30xx cn38xx;
353 struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
354 struct cvmx_iob_ctl_status_cn30xx cn50xx;
355 struct cvmx_iob_ctl_status_cn52xx
356 {
357 #if __BYTE_ORDER == __BIG_ENDIAN
358 uint64_t reserved_6_63 : 58;
359 uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next
360 transaction that could arbitrate for the XMB. */
361 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
362 matchers. PASS2 FIELD. */
363 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
364 matchers. PASS2 FIELD. */
365 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
366 '0' is for big-endian and '1' is for little-endian. */
367 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
368 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
369 big-endian and '1' is for little-endian. */
370 #else
371 uint64_t fau_end : 1;
372 uint64_t dwb_enb : 1;
373 uint64_t pko_enb : 1;
374 uint64_t inb_mat : 1;
375 uint64_t outb_mat : 1;
376 uint64_t rr_mode : 1;
377 uint64_t reserved_6_63 : 58;
378 #endif
379 } cn52xx;
380 struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
381 struct cvmx_iob_ctl_status_cn30xx cn56xx;
382 struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
383 struct cvmx_iob_ctl_status_cn30xx cn58xx;
384 struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
385 struct cvmx_iob_ctl_status_s cn63xx;
386 struct cvmx_iob_ctl_status_s cn63xxp1;
387 };
388 typedef union cvmx_iob_ctl_status cvmx_iob_ctl_status_t;
389
390 /**
391 * cvmx_iob_dwb_pri_cnt
392 *
393 * DWB To CMB Priority Counter = Don't Write Back to CMB Priority Counter Enable and Timer Value
394 *
395 * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C.
396 */
397 union cvmx_iob_dwb_pri_cnt
398 {
399 uint64_t u64;
400 struct cvmx_iob_dwb_pri_cnt_s
401 {
402 #if __BYTE_ORDER == __BIG_ENDIAN
403 uint64_t reserved_16_63 : 48;
404 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
405 when CNT_VAL is reached. */
406 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
407 the priority for access to CMB. */
408 #else
409 uint64_t cnt_val : 15;
410 uint64_t cnt_enb : 1;
411 uint64_t reserved_16_63 : 48;
412 #endif
413 } s;
414 struct cvmx_iob_dwb_pri_cnt_s cn38xx;
415 struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
416 struct cvmx_iob_dwb_pri_cnt_s cn52xx;
417 struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
418 struct cvmx_iob_dwb_pri_cnt_s cn56xx;
419 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
420 struct cvmx_iob_dwb_pri_cnt_s cn58xx;
421 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
422 struct cvmx_iob_dwb_pri_cnt_s cn63xx;
423 struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
424 };
425 typedef union cvmx_iob_dwb_pri_cnt cvmx_iob_dwb_pri_cnt_t;
426
427 /**
428 * cvmx_iob_fau_timeout
429 *
430 * FAU Timeout = Fetch and Add Unit Tag-Switch Timeout
431 *
432 * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out.
433 * for Queue 0.
434 */
435 union cvmx_iob_fau_timeout
436 {
437 uint64_t u64;
438 struct cvmx_iob_fau_timeout_s
439 {
440 #if __BYTE_ORDER == __BIG_ENDIAN
441 uint64_t reserved_13_63 : 51;
442 uint64_t tout_enb : 1; /**< The enable for the FAU timeout feature.
443 '1' will enable the timeout, '0' will disable. */
444 uint64_t tout_val : 12; /**< When a tag request arrives from the PP a timer is
445 started associate with that PP. The timer which
446 increments every 256 eclks is compared to TOUT_VAL.
447 When the two are equal the IOB will flag the tag
448 request to complete as a time-out tag operation.
449 The 256 count timer used to increment the PP
450 associated timer is always running so the first
451 increment of the PP associated timer may occur any
452 where within the first 256 eclks. Note that '0'
453 is an illegal value. */
454 #else
455 uint64_t tout_val : 12;
456 uint64_t tout_enb : 1;
457 uint64_t reserved_13_63 : 51;
458 #endif
459 } s;
460 struct cvmx_iob_fau_timeout_s cn30xx;
461 struct cvmx_iob_fau_timeout_s cn31xx;
462 struct cvmx_iob_fau_timeout_s cn38xx;
463 struct cvmx_iob_fau_timeout_s cn38xxp2;
464 struct cvmx_iob_fau_timeout_s cn50xx;
465 struct cvmx_iob_fau_timeout_s cn52xx;
466 struct cvmx_iob_fau_timeout_s cn52xxp1;
467 struct cvmx_iob_fau_timeout_s cn56xx;
468 struct cvmx_iob_fau_timeout_s cn56xxp1;
469 struct cvmx_iob_fau_timeout_s cn58xx;
470 struct cvmx_iob_fau_timeout_s cn58xxp1;
471 struct cvmx_iob_fau_timeout_s cn63xx;
472 struct cvmx_iob_fau_timeout_s cn63xxp1;
473 };
474 typedef union cvmx_iob_fau_timeout cvmx_iob_fau_timeout_t;
475
476 /**
477 * cvmx_iob_i2c_pri_cnt
478 *
479 * IPD To CMB Store Priority Counter = IPD to CMB Store Priority Counter Enable and Timer Value
480 *
481 * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB.
482 */
483 union cvmx_iob_i2c_pri_cnt
484 {
485 uint64_t u64;
486 struct cvmx_iob_i2c_pri_cnt_s
487 {
488 #if __BYTE_ORDER == __BIG_ENDIAN
489 uint64_t reserved_16_63 : 48;
490 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
491 when CNT_VAL is reached. */
492 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
493 the priority for access to CMB. */
494 #else
495 uint64_t cnt_val : 15;
496 uint64_t cnt_enb : 1;
497 uint64_t reserved_16_63 : 48;
498 #endif
499 } s;
500 struct cvmx_iob_i2c_pri_cnt_s cn38xx;
501 struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
502 struct cvmx_iob_i2c_pri_cnt_s cn52xx;
503 struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
504 struct cvmx_iob_i2c_pri_cnt_s cn56xx;
505 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
506 struct cvmx_iob_i2c_pri_cnt_s cn58xx;
507 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
508 struct cvmx_iob_i2c_pri_cnt_s cn63xx;
509 struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
510 };
511 typedef union cvmx_iob_i2c_pri_cnt cvmx_iob_i2c_pri_cnt_t;
512
513 /**
514 * cvmx_iob_inb_control_match
515 *
516 * IOB_INB_CONTROL_MATCH = IOB Inbound Control Match
517 *
518 * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register
519 */
520 union cvmx_iob_inb_control_match
521 {
522 uint64_t u64;
523 struct cvmx_iob_inb_control_match_s
524 {
525 #if __BYTE_ORDER == __BIG_ENDIAN
526 uint64_t reserved_29_63 : 35;
527 uint64_t mask : 8; /**< Pattern to match on the inbound NCB. */
528 uint64_t opc : 4; /**< Pattern to match on the inbound NCB. */
529 uint64_t dst : 9; /**< Pattern to match on the inbound NCB. */
530 uint64_t src : 8; /**< Pattern to match on the inbound NCB. */
531 #else
532 uint64_t src : 8;
533 uint64_t dst : 9;
534 uint64_t opc : 4;
535 uint64_t mask : 8;
536 uint64_t reserved_29_63 : 35;
537 #endif
538 } s;
539 struct cvmx_iob_inb_control_match_s cn30xx;
540 struct cvmx_iob_inb_control_match_s cn31xx;
541 struct cvmx_iob_inb_control_match_s cn38xx;
542 struct cvmx_iob_inb_control_match_s cn38xxp2;
543 struct cvmx_iob_inb_control_match_s cn50xx;
544 struct cvmx_iob_inb_control_match_s cn52xx;
545 struct cvmx_iob_inb_control_match_s cn52xxp1;
546 struct cvmx_iob_inb_control_match_s cn56xx;
547 struct cvmx_iob_inb_control_match_s cn56xxp1;
548 struct cvmx_iob_inb_control_match_s cn58xx;
549 struct cvmx_iob_inb_control_match_s cn58xxp1;
550 struct cvmx_iob_inb_control_match_s cn63xx;
551 struct cvmx_iob_inb_control_match_s cn63xxp1;
552 };
553 typedef union cvmx_iob_inb_control_match cvmx_iob_inb_control_match_t;
554
555 /**
556 * cvmx_iob_inb_control_match_enb
557 *
558 * IOB_INB_CONTROL_MATCH_ENB = IOB Inbound Control Match Enable
559 *
560 * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register
561 */
562 union cvmx_iob_inb_control_match_enb
563 {
564 uint64_t u64;
565 struct cvmx_iob_inb_control_match_enb_s
566 {
567 #if __BYTE_ORDER == __BIG_ENDIAN
568 uint64_t reserved_29_63 : 35;
569 uint64_t mask : 8; /**< Pattern to match on the inbound NCB. */
570 uint64_t opc : 4; /**< Pattern to match on the inbound NCB. */
571 uint64_t dst : 9; /**< Pattern to match on the inbound NCB. */
572 uint64_t src : 8; /**< Pattern to match on the inbound NCB. */
573 #else
574 uint64_t src : 8;
575 uint64_t dst : 9;
576 uint64_t opc : 4;
577 uint64_t mask : 8;
578 uint64_t reserved_29_63 : 35;
579 #endif
580 } s;
581 struct cvmx_iob_inb_control_match_enb_s cn30xx;
582 struct cvmx_iob_inb_control_match_enb_s cn31xx;
583 struct cvmx_iob_inb_control_match_enb_s cn38xx;
584 struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
585 struct cvmx_iob_inb_control_match_enb_s cn50xx;
586 struct cvmx_iob_inb_control_match_enb_s cn52xx;
587 struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
588 struct cvmx_iob_inb_control_match_enb_s cn56xx;
589 struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
590 struct cvmx_iob_inb_control_match_enb_s cn58xx;
591 struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
592 struct cvmx_iob_inb_control_match_enb_s cn63xx;
593 struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
594 };
595 typedef union cvmx_iob_inb_control_match_enb cvmx_iob_inb_control_match_enb_t;
596
597 /**
598 * cvmx_iob_inb_data_match
599 *
600 * IOB_INB_DATA_MATCH = IOB Inbound Data Match
601 *
602 * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register
603 */
604 union cvmx_iob_inb_data_match
605 {
606 uint64_t u64;
607 struct cvmx_iob_inb_data_match_s
608 {
609 #if __BYTE_ORDER == __BIG_ENDIAN
610 uint64_t data : 64; /**< Pattern to match on the inbound NCB. */
611 #else
612 uint64_t data : 64;
613 #endif
614 } s;
615 struct cvmx_iob_inb_data_match_s cn30xx;
616 struct cvmx_iob_inb_data_match_s cn31xx;
617 struct cvmx_iob_inb_data_match_s cn38xx;
618 struct cvmx_iob_inb_data_match_s cn38xxp2;
619 struct cvmx_iob_inb_data_match_s cn50xx;
620 struct cvmx_iob_inb_data_match_s cn52xx;
621 struct cvmx_iob_inb_data_match_s cn52xxp1;
622 struct cvmx_iob_inb_data_match_s cn56xx;
623 struct cvmx_iob_inb_data_match_s cn56xxp1;
624 struct cvmx_iob_inb_data_match_s cn58xx;
625 struct cvmx_iob_inb_data_match_s cn58xxp1;
626 struct cvmx_iob_inb_data_match_s cn63xx;
627 struct cvmx_iob_inb_data_match_s cn63xxp1;
628 };
629 typedef union cvmx_iob_inb_data_match cvmx_iob_inb_data_match_t;
630
631 /**
632 * cvmx_iob_inb_data_match_enb
633 *
634 * IOB_INB_DATA_MATCH_ENB = IOB Inbound Data Match Enable
635 *
636 * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register
637 */
638 union cvmx_iob_inb_data_match_enb
639 {
640 uint64_t u64;
641 struct cvmx_iob_inb_data_match_enb_s
642 {
643 #if __BYTE_ORDER == __BIG_ENDIAN
644 uint64_t data : 64; /**< Bit to enable match of. */
645 #else
646 uint64_t data : 64;
647 #endif
648 } s;
649 struct cvmx_iob_inb_data_match_enb_s cn30xx;
650 struct cvmx_iob_inb_data_match_enb_s cn31xx;
651 struct cvmx_iob_inb_data_match_enb_s cn38xx;
652 struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
653 struct cvmx_iob_inb_data_match_enb_s cn50xx;
654 struct cvmx_iob_inb_data_match_enb_s cn52xx;
655 struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
656 struct cvmx_iob_inb_data_match_enb_s cn56xx;
657 struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
658 struct cvmx_iob_inb_data_match_enb_s cn58xx;
659 struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
660 struct cvmx_iob_inb_data_match_enb_s cn63xx;
661 struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
662 };
663 typedef union cvmx_iob_inb_data_match_enb cvmx_iob_inb_data_match_enb_t;
664
665 /**
666 * cvmx_iob_int_enb
667 *
668 * IOB_INT_ENB = IOB's Interrupt Enable
669 *
670 * The IOB's interrupt enable register. This is a PASS-2 register.
671 */
672 union cvmx_iob_int_enb
673 {
674 uint64_t u64;
675 struct cvmx_iob_int_enb_s
676 {
677 #if __BYTE_ORDER == __BIG_ENDIAN
678 uint64_t reserved_6_63 : 58;
679 uint64_t p_dat : 1; /**< When set (1) and bit 5 of the IOB_INT_SUM
680 register is asserted the IOB will assert an
681 interrupt. */
682 uint64_t np_dat : 1; /**< When set (1) and bit 4 of the IOB_INT_SUM
683 register is asserted the IOB will assert an
684 interrupt. */
685 uint64_t p_eop : 1; /**< When set (1) and bit 3 of the IOB_INT_SUM
686 register is asserted the IOB will assert an
687 interrupt. */
688 uint64_t p_sop : 1; /**< When set (1) and bit 2 of the IOB_INT_SUM
689 register is asserted the IOB will assert an
690 interrupt. */
691 uint64_t np_eop : 1; /**< When set (1) and bit 1 of the IOB_INT_SUM
692 register is asserted the IOB will assert an
693 interrupt. */
694 uint64_t np_sop : 1; /**< When set (1) and bit 0 of the IOB_INT_SUM
695 register is asserted the IOB will assert an
696 interrupt. */
697 #else
698 uint64_t np_sop : 1;
699 uint64_t np_eop : 1;
700 uint64_t p_sop : 1;
701 uint64_t p_eop : 1;
702 uint64_t np_dat : 1;
703 uint64_t p_dat : 1;
704 uint64_t reserved_6_63 : 58;
705 #endif
706 } s;
707 struct cvmx_iob_int_enb_cn30xx
708 {
709 #if __BYTE_ORDER == __BIG_ENDIAN
710 uint64_t reserved_4_63 : 60;
711 uint64_t p_eop : 1; /**< When set (1) and bit 3 of the IOB_INT_SUM
712 register is asserted the IOB will assert an
713 interrupt. */
714 uint64_t p_sop : 1; /**< When set (1) and bit 2 of the IOB_INT_SUM
715 register is asserted the IOB will assert an
716 interrupt. */
717 uint64_t np_eop : 1; /**< When set (1) and bit 1 of the IOB_INT_SUM
718 register is asserted the IOB will assert an
719 interrupt. */
720 uint64_t np_sop : 1; /**< When set (1) and bit 0 of the IOB_INT_SUM
721 register is asserted the IOB will assert an
722 interrupt. */
723 #else
724 uint64_t np_sop : 1;
725 uint64_t np_eop : 1;
726 uint64_t p_sop : 1;
727 uint64_t p_eop : 1;
728 uint64_t reserved_4_63 : 60;
729 #endif
730 } cn30xx;
731 struct cvmx_iob_int_enb_cn30xx cn31xx;
732 struct cvmx_iob_int_enb_cn30xx cn38xx;
733 struct cvmx_iob_int_enb_cn30xx cn38xxp2;
734 struct cvmx_iob_int_enb_s cn50xx;
735 struct cvmx_iob_int_enb_s cn52xx;
736 struct cvmx_iob_int_enb_s cn52xxp1;
737 struct cvmx_iob_int_enb_s cn56xx;
738 struct cvmx_iob_int_enb_s cn56xxp1;
739 struct cvmx_iob_int_enb_s cn58xx;
740 struct cvmx_iob_int_enb_s cn58xxp1;
741 struct cvmx_iob_int_enb_s cn63xx;
742 struct cvmx_iob_int_enb_s cn63xxp1;
743 };
744 typedef union cvmx_iob_int_enb cvmx_iob_int_enb_t;
745
746 /**
747 * cvmx_iob_int_sum
748 *
749 * IOB_INT_SUM = IOB's Interrupt Summary Register
750 *
751 * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register.
752 */
753 union cvmx_iob_int_sum
754 {
755 uint64_t u64;
756 struct cvmx_iob_int_sum_s
757 {
758 #if __BYTE_ORDER == __BIG_ENDIAN
759 uint64_t reserved_6_63 : 58;
760 uint64_t p_dat : 1; /**< Set when a data arrives before a SOP for the same
761 port for a passthrough packet.
762 The first detected error associated with bits [5:0]
763 of this register will only be set here. A new bit
764 can be set when the previous reported bit is cleared. */
765 uint64_t np_dat : 1; /**< Set when a data arrives before a SOP for the same
766 port for a non-passthrough packet.
767 The first detected error associated with bits [5:0]
768 of this register will only be set here. A new bit
769 can be set when the previous reported bit is cleared. */
770 uint64_t p_eop : 1; /**< Set when a EOP is followed by an EOP for the same
771 port for a passthrough packet.
772 The first detected error associated with bits [5:0]
773 of this register will only be set here. A new bit
774 can be set when the previous reported bit is cleared. */
775 uint64_t p_sop : 1; /**< Set when a SOP is followed by an SOP for the same
776 port for a passthrough packet.
777 The first detected error associated with bits [5:0]
778 of this register will only be set here. A new bit
779 can be set when the previous reported bit is cleared. */
780 uint64_t np_eop : 1; /**< Set when a EOP is followed by an EOP for the same
781 port for a non-passthrough packet.
782 The first detected error associated with bits [5:0]
783 of this register will only be set here. A new bit
784 can be set when the previous reported bit is cleared. */
785 uint64_t np_sop : 1; /**< Set when a SOP is followed by an SOP for the same
786 port for a non-passthrough packet.
787 The first detected error associated with bits [5:0]
788 of this register will only be set here. A new bit
789 can be set when the previous reported bit is cleared. */
790 #else
791 uint64_t np_sop : 1;
792 uint64_t np_eop : 1;
793 uint64_t p_sop : 1;
794 uint64_t p_eop : 1;
795 uint64_t np_dat : 1;
796 uint64_t p_dat : 1;
797 uint64_t reserved_6_63 : 58;
798 #endif
799 } s;
800 struct cvmx_iob_int_sum_cn30xx
801 {
802 #if __BYTE_ORDER == __BIG_ENDIAN
803 uint64_t reserved_4_63 : 60;
804 uint64_t p_eop : 1; /**< Set when a EOP is followed by an EOP for the same
805 port for a passthrough packet.
806 The first detected error associated with bits [3:0]
807 of this register will only be set here. A new bit
808 can be set when the previous reported bit is cleared. */
809 uint64_t p_sop : 1; /**< Set when a SOP is followed by an SOP for the same
810 port for a passthrough packet.
811 The first detected error associated with bits [3:0]
812 of this register will only be set here. A new bit
813 can be set when the previous reported bit is cleared. */
814 uint64_t np_eop : 1; /**< Set when a EOP is followed by an EOP for the same
815 port for a non-passthrough packet.
816 The first detected error associated with bits [3:0]
817 of this register will only be set here. A new bit
818 can be set when the previous reported bit is cleared. */
819 uint64_t np_sop : 1; /**< Set when a SOP is followed by an SOP for the same
820 port for a non-passthrough packet.
821 The first detected error associated with bits [3:0]
822 of this register will only be set here. A new bit
823 can be set when the previous reported bit is cleared. */
824 #else
825 uint64_t np_sop : 1;
826 uint64_t np_eop : 1;
827 uint64_t p_sop : 1;
828 uint64_t p_eop : 1;
829 uint64_t reserved_4_63 : 60;
830 #endif
831 } cn30xx;
832 struct cvmx_iob_int_sum_cn30xx cn31xx;
833 struct cvmx_iob_int_sum_cn30xx cn38xx;
834 struct cvmx_iob_int_sum_cn30xx cn38xxp2;
835 struct cvmx_iob_int_sum_s cn50xx;
836 struct cvmx_iob_int_sum_s cn52xx;
837 struct cvmx_iob_int_sum_s cn52xxp1;
838 struct cvmx_iob_int_sum_s cn56xx;
839 struct cvmx_iob_int_sum_s cn56xxp1;
840 struct cvmx_iob_int_sum_s cn58xx;
841 struct cvmx_iob_int_sum_s cn58xxp1;
842 struct cvmx_iob_int_sum_s cn63xx;
843 struct cvmx_iob_int_sum_s cn63xxp1;
844 };
845 typedef union cvmx_iob_int_sum cvmx_iob_int_sum_t;
846
847 /**
848 * cvmx_iob_n2c_l2c_pri_cnt
849 *
850 * NCB To CMB L2C Priority Counter = NCB to CMB L2C Priority Counter Enable and Timer Value
851 *
852 * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB.
853 */
854 union cvmx_iob_n2c_l2c_pri_cnt
855 {
856 uint64_t u64;
857 struct cvmx_iob_n2c_l2c_pri_cnt_s
858 {
859 #if __BYTE_ORDER == __BIG_ENDIAN
860 uint64_t reserved_16_63 : 48;
861 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
862 when CNT_VAL is reached. */
863 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
864 the priority for access to CMB. */
865 #else
866 uint64_t cnt_val : 15;
867 uint64_t cnt_enb : 1;
868 uint64_t reserved_16_63 : 48;
869 #endif
870 } s;
871 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
872 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
873 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
874 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
875 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
876 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
877 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
878 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
879 struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
880 struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
881 };
882 typedef union cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_l2c_pri_cnt_t;
883
884 /**
885 * cvmx_iob_n2c_rsp_pri_cnt
886 *
887 * NCB To CMB Response Priority Counter = NCB to CMB Response Priority Counter Enable and Timer Value
888 *
889 * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB.
890 */
891 union cvmx_iob_n2c_rsp_pri_cnt
892 {
893 uint64_t u64;
894 struct cvmx_iob_n2c_rsp_pri_cnt_s
895 {
896 #if __BYTE_ORDER == __BIG_ENDIAN
897 uint64_t reserved_16_63 : 48;
898 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
899 when CNT_VAL is reached. */
900 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
901 the priority for access to CMB. */
902 #else
903 uint64_t cnt_val : 15;
904 uint64_t cnt_enb : 1;
905 uint64_t reserved_16_63 : 48;
906 #endif
907 } s;
908 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
909 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
910 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
911 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
912 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
913 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
914 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
915 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
916 struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
917 struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
918 };
919 typedef union cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_n2c_rsp_pri_cnt_t;
920
921 /**
922 * cvmx_iob_outb_com_pri_cnt
923 *
924 * Commit To NCB Priority Counter = Commit to NCB Priority Counter Enable and Timer Value
925 *
926 * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB.
927 */
928 union cvmx_iob_outb_com_pri_cnt
929 {
930 uint64_t u64;
931 struct cvmx_iob_outb_com_pri_cnt_s
932 {
933 #if __BYTE_ORDER == __BIG_ENDIAN
934 uint64_t reserved_16_63 : 48;
935 uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority
936 when CNT_VAL is reached. */
937 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
938 the priority for access to NCB. */
939 #else
940 uint64_t cnt_val : 15;
941 uint64_t cnt_enb : 1;
942 uint64_t reserved_16_63 : 48;
943 #endif
944 } s;
945 struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
946 struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
947 struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
948 struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
949 struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
950 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
951 struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
952 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
953 struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
954 struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
955 };
956 typedef union cvmx_iob_outb_com_pri_cnt cvmx_iob_outb_com_pri_cnt_t;
957
958 /**
959 * cvmx_iob_outb_control_match
960 *
961 * IOB_OUTB_CONTROL_MATCH = IOB Outbound Control Match
962 *
963 * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register
964 */
965 union cvmx_iob_outb_control_match
966 {
967 uint64_t u64;
968 struct cvmx_iob_outb_control_match_s
969 {
970 #if __BYTE_ORDER == __BIG_ENDIAN
971 uint64_t reserved_26_63 : 38;
972 uint64_t mask : 8; /**< Pattern to match on the outbound NCB. */
973 uint64_t eot : 1; /**< Pattern to match on the outbound NCB. */
974 uint64_t dst : 8; /**< Pattern to match on the outbound NCB. */
975 uint64_t src : 9; /**< Pattern to match on the outbound NCB. */
976 #else
977 uint64_t src : 9;
978 uint64_t dst : 8;
979 uint64_t eot : 1;
980 uint64_t mask : 8;
981 uint64_t reserved_26_63 : 38;
982 #endif
983 } s;
984 struct cvmx_iob_outb_control_match_s cn30xx;
985 struct cvmx_iob_outb_control_match_s cn31xx;
986 struct cvmx_iob_outb_control_match_s cn38xx;
987 struct cvmx_iob_outb_control_match_s cn38xxp2;
988 struct cvmx_iob_outb_control_match_s cn50xx;
989 struct cvmx_iob_outb_control_match_s cn52xx;
990 struct cvmx_iob_outb_control_match_s cn52xxp1;
991 struct cvmx_iob_outb_control_match_s cn56xx;
992 struct cvmx_iob_outb_control_match_s cn56xxp1;
993 struct cvmx_iob_outb_control_match_s cn58xx;
994 struct cvmx_iob_outb_control_match_s cn58xxp1;
995 struct cvmx_iob_outb_control_match_s cn63xx;
996 struct cvmx_iob_outb_control_match_s cn63xxp1;
997 };
998 typedef union cvmx_iob_outb_control_match cvmx_iob_outb_control_match_t;
999
1000 /**
1001 * cvmx_iob_outb_control_match_enb
1002 *
1003 * IOB_OUTB_CONTROL_MATCH_ENB = IOB Outbound Control Match Enable
1004 *
1005 * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register
1006 */
1007 union cvmx_iob_outb_control_match_enb
1008 {
1009 uint64_t u64;
1010 struct cvmx_iob_outb_control_match_enb_s
1011 {
1012 #if __BYTE_ORDER == __BIG_ENDIAN
1013 uint64_t reserved_26_63 : 38;
1014 uint64_t mask : 8; /**< Pattern to match on the outbound NCB. */
1015 uint64_t eot : 1; /**< Pattern to match on the outbound NCB. */
1016 uint64_t dst : 8; /**< Pattern to match on the outbound NCB. */
1017 uint64_t src : 9; /**< Pattern to match on the outbound NCB. */
1018 #else
1019 uint64_t src : 9;
1020 uint64_t dst : 8;
1021 uint64_t eot : 1;
1022 uint64_t mask : 8;
1023 uint64_t reserved_26_63 : 38;
1024 #endif
1025 } s;
1026 struct cvmx_iob_outb_control_match_enb_s cn30xx;
1027 struct cvmx_iob_outb_control_match_enb_s cn31xx;
1028 struct cvmx_iob_outb_control_match_enb_s cn38xx;
1029 struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
1030 struct cvmx_iob_outb_control_match_enb_s cn50xx;
1031 struct cvmx_iob_outb_control_match_enb_s cn52xx;
1032 struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
1033 struct cvmx_iob_outb_control_match_enb_s cn56xx;
1034 struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
1035 struct cvmx_iob_outb_control_match_enb_s cn58xx;
1036 struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
1037 struct cvmx_iob_outb_control_match_enb_s cn63xx;
1038 struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
1039 };
1040 typedef union cvmx_iob_outb_control_match_enb cvmx_iob_outb_control_match_enb_t;
1041
1042 /**
1043 * cvmx_iob_outb_data_match
1044 *
1045 * IOB_OUTB_DATA_MATCH = IOB Outbound Data Match
1046 *
1047 * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register
1048 */
1049 union cvmx_iob_outb_data_match
1050 {
1051 uint64_t u64;
1052 struct cvmx_iob_outb_data_match_s
1053 {
1054 #if __BYTE_ORDER == __BIG_ENDIAN
1055 uint64_t data : 64; /**< Pattern to match on the outbound NCB. */
1056 #else
1057 uint64_t data : 64;
1058 #endif
1059 } s;
1060 struct cvmx_iob_outb_data_match_s cn30xx;
1061 struct cvmx_iob_outb_data_match_s cn31xx;
1062 struct cvmx_iob_outb_data_match_s cn38xx;
1063 struct cvmx_iob_outb_data_match_s cn38xxp2;
1064 struct cvmx_iob_outb_data_match_s cn50xx;
1065 struct cvmx_iob_outb_data_match_s cn52xx;
1066 struct cvmx_iob_outb_data_match_s cn52xxp1;
1067 struct cvmx_iob_outb_data_match_s cn56xx;
1068 struct cvmx_iob_outb_data_match_s cn56xxp1;
1069 struct cvmx_iob_outb_data_match_s cn58xx;
1070 struct cvmx_iob_outb_data_match_s cn58xxp1;
1071 struct cvmx_iob_outb_data_match_s cn63xx;
1072 struct cvmx_iob_outb_data_match_s cn63xxp1;
1073 };
1074 typedef union cvmx_iob_outb_data_match cvmx_iob_outb_data_match_t;
1075
1076 /**
1077 * cvmx_iob_outb_data_match_enb
1078 *
1079 * IOB_OUTB_DATA_MATCH_ENB = IOB Outbound Data Match Enable
1080 *
1081 * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register
1082 */
1083 union cvmx_iob_outb_data_match_enb
1084 {
1085 uint64_t u64;
1086 struct cvmx_iob_outb_data_match_enb_s
1087 {
1088 #if __BYTE_ORDER == __BIG_ENDIAN
1089 uint64_t data : 64; /**< Bit to enable match of. */
1090 #else
1091 uint64_t data : 64;
1092 #endif
1093 } s;
1094 struct cvmx_iob_outb_data_match_enb_s cn30xx;
1095 struct cvmx_iob_outb_data_match_enb_s cn31xx;
1096 struct cvmx_iob_outb_data_match_enb_s cn38xx;
1097 struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
1098 struct cvmx_iob_outb_data_match_enb_s cn50xx;
1099 struct cvmx_iob_outb_data_match_enb_s cn52xx;
1100 struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
1101 struct cvmx_iob_outb_data_match_enb_s cn56xx;
1102 struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
1103 struct cvmx_iob_outb_data_match_enb_s cn58xx;
1104 struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
1105 struct cvmx_iob_outb_data_match_enb_s cn63xx;
1106 struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
1107 };
1108 typedef union cvmx_iob_outb_data_match_enb cvmx_iob_outb_data_match_enb_t;
1109
1110 /**
1111 * cvmx_iob_outb_fpa_pri_cnt
1112 *
1113 * FPA To NCB Priority Counter = FPA Returns to NCB Priority Counter Enable and Timer Value
1114 *
1115 * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB.
1116 */
1117 union cvmx_iob_outb_fpa_pri_cnt
1118 {
1119 uint64_t u64;
1120 struct cvmx_iob_outb_fpa_pri_cnt_s
1121 {
1122 #if __BYTE_ORDER == __BIG_ENDIAN
1123 uint64_t reserved_16_63 : 48;
1124 uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority
1125 when CNT_VAL is reached. */
1126 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1127 the priority for access to NCB. */
1128 #else
1129 uint64_t cnt_val : 15;
1130 uint64_t cnt_enb : 1;
1131 uint64_t reserved_16_63 : 48;
1132 #endif
1133 } s;
1134 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
1135 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
1136 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
1137 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
1138 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
1139 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
1140 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
1141 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
1142 struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
1143 struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
1144 };
1145 typedef union cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_fpa_pri_cnt_t;
1146
1147 /**
1148 * cvmx_iob_outb_req_pri_cnt
1149 *
1150 * Request To NCB Priority Counter = Request to NCB Priority Counter Enable and Timer Value
1151 *
1152 * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB.
1153 */
1154 union cvmx_iob_outb_req_pri_cnt
1155 {
1156 uint64_t u64;
1157 struct cvmx_iob_outb_req_pri_cnt_s
1158 {
1159 #if __BYTE_ORDER == __BIG_ENDIAN
1160 uint64_t reserved_16_63 : 48;
1161 uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority
1162 when CNT_VAL is reached. */
1163 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1164 the priority for access to NCB. */
1165 #else
1166 uint64_t cnt_val : 15;
1167 uint64_t cnt_enb : 1;
1168 uint64_t reserved_16_63 : 48;
1169 #endif
1170 } s;
1171 struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
1172 struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
1173 struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
1174 struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
1175 struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
1176 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
1177 struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
1178 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
1179 struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
1180 struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
1181 };
1182 typedef union cvmx_iob_outb_req_pri_cnt cvmx_iob_outb_req_pri_cnt_t;
1183
1184 /**
1185 * cvmx_iob_p2c_req_pri_cnt
1186 *
1187 * PKO To CMB Response Priority Counter = PKO to CMB Response Priority Counter Enable and Timer Value
1188 *
1189 * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB.
1190 */
1191 union cvmx_iob_p2c_req_pri_cnt
1192 {
1193 uint64_t u64;
1194 struct cvmx_iob_p2c_req_pri_cnt_s
1195 {
1196 #if __BYTE_ORDER == __BIG_ENDIAN
1197 uint64_t reserved_16_63 : 48;
1198 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
1199 when CNT_VAL is reached. */
1200 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1201 the priority for access to CMB. */
1202 #else
1203 uint64_t cnt_val : 15;
1204 uint64_t cnt_enb : 1;
1205 uint64_t reserved_16_63 : 48;
1206 #endif
1207 } s;
1208 struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
1209 struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
1210 struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
1211 struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
1212 struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
1213 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
1214 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
1215 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
1216 struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
1217 struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
1218 };
1219 typedef union cvmx_iob_p2c_req_pri_cnt cvmx_iob_p2c_req_pri_cnt_t;
1220
1221 /**
1222 * cvmx_iob_pkt_err
1223 *
1224 * IOB_PKT_ERR = IOB Packet Error Register
1225 *
1226 * Provides status about the failing packet recevie error. This is a PASS-2 register.
1227 */
1228 union cvmx_iob_pkt_err
1229 {
1230 uint64_t u64;
1231 struct cvmx_iob_pkt_err_s
1232 {
1233 #if __BYTE_ORDER == __BIG_ENDIAN
1234 uint64_t reserved_12_63 : 52;
1235 uint64_t vport : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field
1236 latches the failing vport associate with the
1237 IOB_INT_SUM[3:0] bit set. */
1238 uint64_t port : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field
1239 latches the failing port associate with the
1240 IOB_INT_SUM[3:0] bit set. */
1241 #else
1242 uint64_t port : 6;
1243 uint64_t vport : 6;
1244 uint64_t reserved_12_63 : 52;
1245 #endif
1246 } s;
1247 struct cvmx_iob_pkt_err_cn30xx
1248 {
1249 #if __BYTE_ORDER == __BIG_ENDIAN
1250 uint64_t reserved_6_63 : 58;
1251 uint64_t port : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field
1252 latches the failing port associate with the
1253 IOB_INT_SUM[3:0] bit set. */
1254 #else
1255 uint64_t port : 6;
1256 uint64_t reserved_6_63 : 58;
1257 #endif
1258 } cn30xx;
1259 struct cvmx_iob_pkt_err_cn30xx cn31xx;
1260 struct cvmx_iob_pkt_err_cn30xx cn38xx;
1261 struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
1262 struct cvmx_iob_pkt_err_cn30xx cn50xx;
1263 struct cvmx_iob_pkt_err_cn30xx cn52xx;
1264 struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
1265 struct cvmx_iob_pkt_err_cn30xx cn56xx;
1266 struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
1267 struct cvmx_iob_pkt_err_cn30xx cn58xx;
1268 struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
1269 struct cvmx_iob_pkt_err_s cn63xx;
1270 struct cvmx_iob_pkt_err_s cn63xxp1;
1271 };
1272 typedef union cvmx_iob_pkt_err cvmx_iob_pkt_err_t;
1273
1274 /**
1275 * cvmx_iob_to_cmb_credits
1276 *
1277 * IOB_TO_CMB_CREDITS = IOB To CMB Credits
1278 *
1279 * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
1280 */
1281 union cvmx_iob_to_cmb_credits
1282 {
1283 uint64_t u64;
1284 struct cvmx_iob_to_cmb_credits_s
1285 {
1286 #if __BYTE_ORDER == __BIG_ENDIAN
1287 uint64_t reserved_9_63 : 55;
1288 uint64_t pko_rd : 3; /**< Number of PKO reads that can be out to L2C where
1289 0 == 8-credits. */
1290 uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where
1291 0 == 8-credits. */
1292 uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C
1293 where 0 == 8-credits. */
1294 #else
1295 uint64_t ncb_wr : 3;
1296 uint64_t ncb_rd : 3;
1297 uint64_t pko_rd : 3;
1298 uint64_t reserved_9_63 : 55;
1299 #endif
1300 } s;
1301 struct cvmx_iob_to_cmb_credits_s cn52xx;
1302 struct cvmx_iob_to_cmb_credits_s cn63xx;
1303 struct cvmx_iob_to_cmb_credits_s cn63xxp1;
1304 };
1305 typedef union cvmx_iob_to_cmb_credits cvmx_iob_to_cmb_credits_t;
1306
1307 #endif
1308