Searched refs:BIT_31 (Results 1 – 6 of 6) sorted by relevance
85 #define BIT_31 (0x1 << 31) macro174 #define Q81_CTL_PROC_ADDR_RDY BIT_31368 #define Q81_CTL_FLASH_ADDR_RDY BIT_31386 #define Q81_CTL_MAC_PROTO_AI_MW BIT_31444 #define Q81_CTL_RI_MW BIT_31504 #define Q81_CTL_RD_RSS_MATCH BIT_31
543 #define Q81_XG_SERDES_ADDR_RDY BIT_31574 #define Q81_XGMAC_ADDR_RDY BIT_31
159 #define BIT_31 (1 << 31) macro261 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */310 #define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */343 #define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */826 #define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */996 #define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */1008 #define I2C_FLAG BIT_31 /* Start read/write if WR */1048 #define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */1095 #define BMU_IDLE BIT_31 /* BMU Idle State */1128 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/[all …]
69 #define BIT_31 (0x1 << 31) macro
450 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31