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/freebsd-14-stable/sys/crypto/openssl/aarch64/
HDghashv8-armx.S12 ld1 {v17.2d},[x1] //load input H
15 ext v3.16b,v17.16b,v17.16b,#8
17 dup v17.4s,v17.s[1]
20 sshr v17.4s,v17.4s,#31 //broadcast carry bit
24 and v16.16b,v16.16b,v17.16b
36 ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
38 eor v1.16b,v1.16b,v17.16b
51 ext v17.16b,v22.16b,v22.16b,#8 //Karatsuba pre-processing
52 eor v17.16b,v17.16b,v22.16b
53 ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
[all …]
HDaesv8-armx.S304 ld1 {v16.4s,v17.4s},[x3],#32 // load key schedule...
313 aese v0.16b,v17.16b
315 ld1 {v17.4s},[x3],#16 // load key schedule...
322 aese v0.16b,v17.16b
344 ld1 {v16.4s,v17.4s},[x3],#32 // load key schedule...
353 aesd v0.16b,v17.16b
355 ld1 {v17.4s},[x3],#16 // load key schedule...
362 aesd v0.16b,v17.16b
393 ld1 {v16.4s,v17.4s},[x3] // load key schedule...
437 aese v0.16b,v17.16b
[all …]
HDchacha-armv8.S359 dup v17.4s,v1.s[0]
389 add v16.4s,v16.4s,v17.4s
421 eor v4.16b,v17.16b,v18.16b
429 ushr v17.4s,v4.4s,#20
437 sli v17.4s,v4.4s,#12
445 add v16.4s,v16.4s,v17.4s
477 eor v4.16b,v17.16b,v18.16b
485 ushr v17.4s,v4.4s,#25
489 sli v17.4s,v4.4s,#7
499 add v28.4s,v28.4s,v17.4s
[all …]
HDsha256-armv8.S1090 ld1 {v17.4s},[x3],#16
1098 add v17.4s,v17.4s,v5.4s
1104 ld1 {v17.4s},[x3],#16
1112 add v17.4s,v17.4s,v7.4s
1118 ld1 {v17.4s},[x3],#16
1126 add v17.4s,v17.4s,v5.4s
1132 ld1 {v17.4s},[x3],#16
1140 add v17.4s,v17.4s,v7.4s
1146 ld1 {v17.4s},[x3],#16
1154 add v17.4s,v17.4s,v5.4s
[all …]
HDpoly1305-armv8.S537 umlal v23.2d,v17.2s,v1.s[2]
539 umlal v22.2d,v17.2s,v0.s[2]
541 umlal v21.2d,v17.2s,v8.s[2]
543 umlal v20.2d,v17.2s,v6.s[2]
545 umlal v19.2d,v17.2s,v4.s[2]
681 add v17.2s,v12.2s,v27.2s
700 dup v17.2d,v17.d[0]
708 umlal2 v22.2d,v17.4s,v0.4s
709 umlal2 v23.2d,v17.4s,v1.4s
710 umlal2 v19.2d,v17.4s,v4.4s
[all …]
HDvpaes-armv8.S106 movi v17.16b, #0x0f
136 and v1.16b, v7.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
169 and v1.16b, v0.16b, v17.16b // vpand %xmm0, %xmm9, %xmm1 # 0 = k
223 and v1.16b, v14.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
225 and v9.16b, v15.16b, v17.16b
275 and v1.16b, v0.16b, v17.16b // vpand %xmm0, %xmm9, %xmm1 # 0 = k
277 and v9.16b, v8.16b, v17.16b
324 movi v17.16b, #0x0f
353 and v1.16b, v7.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
403 and v1.16b, v0.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1 # 0 = k
[all …]
HDsha512-armv8.S1099 ld1 {v16.16b,v17.16b,v18.16b,v19.16b},[x1],#64 // load input
1106 rev64 v17.16b,v17.16b
1137 add v25.2d,v25.2d,v17.2d
1180 ext v7.16b,v16.16b,v17.16b,#8
1192 ext v7.16b,v17.16b,v18.16b,#8
1233 add v25.2d,v25.2d,v17.2d
1276 ext v7.16b,v16.16b,v17.16b,#8
1288 ext v7.16b,v17.16b,v18.16b,#8
1329 add v25.2d,v25.2d,v17.2d
1372 ext v7.16b,v16.16b,v17.16b,#8
[all …]
HDaes-gcm-armv8_64.S103 trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
133 eor v17.16b, v17.16b, v9.16b //h4k | h3k
361 mov d10, v17.d[1] //GHASH block 4k - mid
381 pmull v30.1q, v30.1d, v17.1d //GHASH block 4k+1 - mid
590 mov d10, v17.d[1] //GHASH block 4k - mid
604 pmull v30.1q, v30.1d, v17.1d //GHASH block 4k+1 - mid
816 mov d10, v17.d[1] //GHASH final-3 block - mid
854 pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
1181 trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
1201 eor v17.16b, v17.16b, v9.16b //h4k | h3k
[all …]
HDsha1-armv8.S1089 ld1 {v16.4s,v17.4s,v18.4s,v19.4s},[x4]
1119 add v21.4s,v17.4s,v5.4s
1124 add v20.4s,v17.4s,v6.4s
1129 add v21.4s,v17.4s,v7.4s
1134 add v20.4s,v17.4s,v4.4s
1139 add v21.4s,v17.4s,v5.4s
HDkeccak1600-armv8.S870 eor v17.16b,v17.16b,v31.16b
/freebsd-14-stable/sys/contrib/openzfs/module/icp/asm-aarch64/blake3/
HDb3_aarch64_sse41.S172 ld2 { v16.4s, v17.4s }, [x8]
183 ext v18.16b, v17.16b, v17.16b, #12
185 mov v17.16b, v18.16b
188 mov v17.s[1], v16.s[2]
216 trn2 v3.4s, v3.4s, v17.4s
220 ushr v17.4s, v5.4s, #12
222 orr v5.16b, v5.16b, v17.16b
223 zip1 v17.2d, v18.2d, v2.2d
226 mov v17.s[3], v16.s[3]
234 ext v4.16b, v17.16b, v17.16b, #12
[all …]
HDb3_aarch64_sse2.S157 ushr v17.4s, v5.4s, #12
159 orr v5.16b, v5.16b, v17.16b
162 ushr v17.4s, v3.4s, #8
164 orr v3.16b, v3.16b, v17.16b
165 ext v17.16b, v18.16b, v1.16b, #8
167 uzp2 v17.4s, v17.4s, v0.4s
170 add v2.4s, v2.4s, v17.4s
221 ext v7.16b, v17.16b, v17.16b, #4
223 uzp1 v17.4s, v7.4s, v7.4s
227 ext v16.16b, v17.16b, v7.16b, #8
[all …]
/freebsd-14-stable/sys/contrib/openzfs/module/icp/asm-aarch64/sha2/
HDsha256-armv8.S1047 ld1 {v17.4s},[x3],#16
1055 add v17.4s,v17.4s,v5.4s
1061 ld1 {v17.4s},[x3],#16
1069 add v17.4s,v17.4s,v7.4s
1075 ld1 {v17.4s},[x3],#16
1083 add v17.4s,v17.4s,v5.4s
1089 ld1 {v17.4s},[x3],#16
1097 add v17.4s,v17.4s,v7.4s
1103 ld1 {v17.4s},[x3],#16
1111 add v17.4s,v17.4s,v5.4s
[all …]
HDsha512-armv8.S1067 rev64 v17.16b,v17.16b
1098 add v25.2d,v25.2d,v17.2d
1141 ext v7.16b,v16.16b,v17.16b,#8
1153 ext v7.16b,v17.16b,v18.16b,#8
1194 add v25.2d,v25.2d,v17.2d
1237 ext v7.16b,v16.16b,v17.16b,#8
1249 ext v7.16b,v17.16b,v18.16b,#8
1290 add v25.2d,v25.2d,v17.2d
1333 ext v7.16b,v16.16b,v17.16b,#8
1345 ext v7.16b,v17.16b,v18.16b,#8
[all …]
/freebsd-14-stable/lib/libpmc/pmu-events/arch/x86/
HDmapfile.csv3 GenuineIntel-6-3D,v17,broadwell,core
4 GenuineIntel-6-47,v17,broadwell,core
17 GenuineIntel-6-3F,v17,haswellx,core
/freebsd-14-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
HDtsan_ppc_regs.h82 #define v17 17 macro
/freebsd-14-stable/contrib/llvm-project/lldb/source/Utility/
HDARM64_DWARF_Registers.h98 v17, enumerator
HDARM64_ehframe_Registers.h97 v17, enumerator
/freebsd-14-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
HDRegisterContextFreeBSD_powerpc.cpp151 uint32_t v17[4]; member
HDRegisterInfos_arm64.h633 DEFINE_VREG(v17),
667 DEFINE_FPU_PSEUDO(s17, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v17),
700 DEFINE_FPU_PSEUDO(d17, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v17),
HDRegisterInfos_riscv64.h169 DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
HDRegisterInfos_powerpc.h147 DEFINE_VMX(v17, LLDB_INVALID_REGNUM), \
HDRegisterInfos_arm64_sve.h428 DEFINE_VREG_SVE(v17, z17),
HDRegisterContextDarwin_arm64.cpp808 case arm64_dwarf::v17: in ConvertRegisterKindToRegisterNumber()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonRegisterInfo.td240 def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>;

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