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/freebsd-14-stable/sys/dev/cpufreq/
HDichss.c62 struct cf_setting sets[2]; /* Only two settings. */ member
98 static int ichss_settings(device_t dev, struct cf_setting *sets,
271 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
272 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
273 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
274 sc->sets[0].lat = 1000; in ichss_attach()
275 sc->sets[0].dev = dev; in ichss_attach()
276 sc->sets[1] = sc->sets[0]; in ichss_attach()
290 ichss_settings(device_t dev, struct cf_setting *sets, int *count) in ichss_settings() argument
296 if (sets == NULL || count == NULL) in ichss_settings()
[all …]
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/amd/
HDamd-seattle-cpus.dtsi51 i-cache-sets = <256>;
54 d-cache-sets = <256>;
67 i-cache-sets = <256>;
70 d-cache-sets = <256>;
82 i-cache-sets = <256>;
85 d-cache-sets = <256>;
97 i-cache-sets = <256>;
100 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
[all …]
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/amazon/
HDalpine-v3.dtsi30 d-cache-sets = <256>;
33 i-cache-sets = <256>;
44 d-cache-sets = <256>;
47 i-cache-sets = <256>;
58 d-cache-sets = <256>;
61 i-cache-sets = <256>;
72 d-cache-sets = <256>;
75 i-cache-sets = <256>;
86 d-cache-sets = <256>;
89 i-cache-sets = <256>;
[all …]
/freebsd-14-stable/sys/x86/cpufreq/
HDsmist.c74 struct cf_setting sets[2]; /* Only two settings. */ member
83 static int smist_settings(device_t dev, struct cf_setting *sets,
392 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; in smist_attach()
393 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; in smist_attach()
394 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; in smist_attach()
395 sc->sets[0].lat = 1000; in smist_attach()
396 sc->sets[0].dev = dev; in smist_attach()
397 sc->sets[1] = sc->sets[0]; in smist_attach()
412 smist_settings(device_t dev, struct cf_setting *sets, int *count) in smist_settings() argument
418 if (sets == NULL || count == NULL) in smist_settings()
[all …]
/freebsd-14-stable/sys/powerpc/cpufreq/
HDdfs.c47 static int dfs_settings(device_t dev, struct cf_setting *sets, int *count);
139 dfs_settings(device_t dev, struct cf_setting *sets, int *count) in dfs_settings() argument
146 if (sets == NULL || count == NULL) in dfs_settings()
152 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * states); in dfs_settings()
154 sets[0].freq = 10000; sets[0].dev = dev; in dfs_settings()
155 sets[1].freq = 5000; sets[1].dev = dev; in dfs_settings()
157 sets[2].freq = 2500; in dfs_settings()
158 sets[2].dev = dev; in dfs_settings()
HDpmufreq.c55 static int pmufreq_settings(device_t dev, struct cf_setting *sets, int *count);
146 pmufreq_settings(device_t dev, struct cf_setting *sets, int *count) in pmufreq_settings() argument
151 if (sets == NULL || count == NULL) in pmufreq_settings()
157 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * 2); in pmufreq_settings()
159 sets[0].freq = sc->maxfreq; sets[0].dev = dev; in pmufreq_settings()
160 sets[1].freq = sc->minfreq; sets[1].dev = dev; in pmufreq_settings()
162 sets[0].lat = INT_MAX; in pmufreq_settings()
163 sets[1].lat = INT_MAX; in pmufreq_settings()
HDpcr.c50 static int pcr_settings(device_t dev, struct cf_setting *sets, int *count);
235 pcr_settings(device_t dev, struct cf_setting *sets, int *count) in pcr_settings() argument
240 if (sets == NULL || count == NULL) in pcr_settings()
246 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->nmodes); in pcr_settings()
248 sets[0].freq = 10000; sets[0].dev = dev; in pcr_settings()
249 sets[1].freq = 5000; sets[1].dev = dev; in pcr_settings()
251 sets[2].freq = 2500; in pcr_settings()
252 sets[2].dev = dev; in pcr_settings()
HDpmcr.c87 static int pmcr_settings(device_t dev, struct cf_setting *sets, int *count);
156 pmcr_settings(device_t dev, struct cf_setting *sets, int *count) in pmcr_settings() argument
160 if (sets == NULL || count == NULL) in pmcr_settings()
166 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * npstates); in pmcr_settings()
169 sets[i].freq = pstate_freqs[i]; in pmcr_settings()
170 sets[i].spec[0] = pstate_ids[i]; in pmcr_settings()
171 sets[i].spec[1] = i; in pmcr_settings()
172 sets[i].dev = dev; in pmcr_settings()
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/marvell/
HDarmada-ap807-quad.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
57 i-cache-sets = <256>;
60 d-cache-sets = <256>;
72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
83 cache-sets = <512>;
91 cache-sets = <512>;
HDarmada-ap806-quad.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
57 i-cache-sets = <256>;
60 d-cache-sets = <256>;
72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
83 cache-sets = <512>;
91 cache-sets = <512>;
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/ti/
HDk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
99 cache-sets = <512>;
109 cache-sets = <512>;
HDk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
88 i-cache-sets = <256>;
91 d-cache-sets = <128>;
102 cache-sets = <512>;
HDk3-j784s4.dtsi72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
86 i-cache-sets = <256>;
89 d-cache-sets = <256>;
100 i-cache-sets = <256>;
103 d-cache-sets = <256>;
114 i-cache-sets = <256>;
117 d-cache-sets = <256>;
128 i-cache-sets = <256>;
131 d-cache-sets = <256>;
[all …]
HDk3-am625.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
62 i-cache-sets = <256>;
65 d-cache-sets = <128>;
78 i-cache-sets = <256>;
81 d-cache-sets = <128>;
94 i-cache-sets = <256>;
97 d-cache-sets = <128>;
153 cache-sets = <512>;
/freebsd-14-stable/sys/contrib/device-tree/src/riscv/sifive/
HDfu540-c000.dtsi29 i-cache-sets = <128>;
43 d-cache-sets = <64>;
45 d-tlb-sets = <1>;
49 i-cache-sets = <64>;
51 i-tlb-sets = <1>;
67 d-cache-sets = <64>;
69 d-tlb-sets = <1>;
73 i-cache-sets = <64>;
75 i-tlb-sets = <1>;
91 d-cache-sets = <64>;
[all …]
HDfu740-c000.dtsi29 i-cache-sets = <128>;
44 d-cache-sets = <64>;
46 d-tlb-sets = <1>;
50 i-cache-sets = <128>;
52 i-tlb-sets = <1>;
68 d-cache-sets = <64>;
70 d-tlb-sets = <1>;
74 i-cache-sets = <128>;
76 i-tlb-sets = <1>;
92 d-cache-sets = <64>;
[all …]
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/arm/
HDfvp-base-revc.dts52 i-cache-sets = <256>;
55 d-cache-sets = <256>;
65 i-cache-sets = <256>;
68 d-cache-sets = <256>;
78 i-cache-sets = <256>;
81 d-cache-sets = <256>;
91 i-cache-sets = <256>;
94 d-cache-sets = <256>;
104 i-cache-sets = <256>;
107 d-cache-sets = <256>;
[all …]
HDjuno-r1.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
146 i-cache-sets = <256>;
149 d-cache-sets = <128>;
163 i-cache-sets = <256>;
166 d-cache-sets = <128>;
[all …]
HDjuno.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
169 d-cache-sets = <128>;
[all …]
HDjuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
170 d-cache-sets = <128>;
[all …]
/freebsd-14-stable/sys/contrib/device-tree/src/arm/
HDbcm2837.dtsi42 /* Source for d/i-cache-line-size and d/i-cache-sets
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
109 /* Source for cache-line-size + cache-sets
[all …]
HDbcm2836.dtsi43 /* Source for d/i-cache-line-size and d/i-cache-sets
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
107 /* Source for cache-line-size + cache-sets
[all …]
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/freescale/
HDimx8qm.dtsi68 i-cache-sets = <256>;
71 d-cache-sets = <128>;
82 i-cache-sets = <256>;
85 d-cache-sets = <128>;
96 i-cache-sets = <256>;
99 d-cache-sets = <128>;
110 i-cache-sets = <256>;
113 d-cache-sets = <128>;
124 i-cache-sets = <256>;
127 d-cache-sets = <256>;
[all …]
/freebsd-14-stable/lib/libc/regex/
HDregfree.c73 if (g->sets != NULL) { in regfree()
75 free(g->sets[i].ranges); in regfree()
76 free(g->sets[i].wides); in regfree()
77 free(g->sets[i].types); in regfree()
79 free((char *)g->sets); in regfree()
/freebsd-14-stable/sys/kern/
HDkern_cpu.c84 struct cf_setting sets[MAX_SETTINGS]; member
111 struct cf_setting *sets, int count);
580 struct cf_setting *sets; in cpufreq_add_levels() local
605 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); in cpufreq_add_levels()
606 if (sets == NULL) in cpufreq_add_levels()
610 error = CPUFREQ_DRV_SETTINGS(dev, sets, &set_count); in cpufreq_add_levels()
617 error = cpufreq_insert_abs(sc, sets, set_count); in cpufreq_add_levels()
626 bcopy(sets, set_arr->sets, set_count * sizeof(*sets)); in cpufreq_add_levels()
635 free(sets, M_TEMP); in cpufreq_add_levels()
738 cpufreq_insert_abs(struct cpufreq_softc *sc, struct cf_setting *sets, in cpufreq_insert_abs() argument
[all …]

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