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Searched refs:rtw89_write32_mask (Results 1 – 22 of 22) sorted by relevance

/freebsd-14-stable/sys/contrib/dev/rtw89/
HDphy_be.c327 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMT_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
329 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMTBF_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
331 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_BYRATE_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
333 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_RULMT_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
335 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_SW_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
349 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_LISTEN_PATH_EN, 0x2); in rtw89_phy_bb_wrap_listen_path_en_init()
358 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_LMT_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
360 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RATE_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
362 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ENON, 0); in rtw89_phy_bb_wrap_force_cr_init()
363 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
[all …]
HDmac_be.c852 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK, in scheduler_init_be()
856 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK, in scheduler_init_be()
861 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32); in scheduler_init_be()
862 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US); in scheduler_init_be()
1008 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12); in tmac_init_be()
1009 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe); in tmac_init_be()
1059 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); in trxptcl_init_be()
1074 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1); in trxptcl_init_be()
1085 rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK, in rst_bacam_be()
1135 rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len); in rmac_init_be()
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HDmac.c389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_mac_dump_dmac_err_status()
391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_mac_dump_dmac_err_status()
393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_mac_dump_dmac_err_status()
396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in rtw89_mac_dump_dmac_err_status()
1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, in hfc_h2c_cfg_ax()
2146 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); in preload_init_set()
2152 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); in preload_init_set()
2153 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); in preload_init_set()
2208 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, in _patch_ss2f_path()
2289 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, in sec_eng_init_ax()
[all …]
HDrtw8852b.c279 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); in rtw8852b_pwr_on_func()
280 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); in rtw8852b_pwr_on_func()
354 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); in rtw8852b_pwr_on_func()
355 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); in rtw8852b_pwr_on_func()
377 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, in rtw8852b_pwr_on_func()
441 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); in rtw8852b_pwr_off_func()
HDpci_be.c59 rtw89_write32_mask(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_CLK_REQ_LAT_MASK, in rtw89_pci_clkreq_set_be()
158 rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1, in rtw89_pci_ctrl_trxdma_pcie_be()
312 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1); in rtw89_pci_ser_setting_be()
471 rtw89_write32_mask(rtwdev, R_BE_PCIE_MIT0_TMR, in rtw89_pci_configure_mit_be()
HDrtw8852bt.c256 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_OCP_L1_MASK, 7); in rtw8852bt_pwr_on_func()
334 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); in rtw8852bt_pwr_on_func()
335 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); in rtw8852bt_pwr_on_func()
351 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, in rtw8852bt_pwr_on_func()
413 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); in rtw8852bt_pwr_off_func()
HDrtw8922a.c864 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
866 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
870 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f); in rtw8922a_set_channel_mac()
872 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e); in rtw8922a_set_channel_mac()
1547 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9); in rtw8922a_bb_preinit()
1548 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1549 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1550 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1); in rtw8922a_bb_preinit()
1551 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx], rdy); in rtw8922a_bb_preinit()
1552 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0); in rtw8922a_bb_preinit()
[all …]
HDpci.c2850 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, in rtw89_pci_mode_op()
2855 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst); in rtw89_pci_mode_op()
2856 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst); in rtw89_pci_mode_op()
2858 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst); in rtw89_pci_mode_op()
2859 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst); in rtw89_pci_mode_op()
2874 rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask, in rtw89_pci_mode_op()
2878 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, in rtw89_pci_mode_op()
2880 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, in rtw89_pci_mode_op()
2883 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK, in rtw89_pci_mode_op()
2885 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK, in rtw89_pci_mode_op()
[all …]
HDrtw8852c.c219 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, in rtw8852c_pwr_on_func()
318 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, in rtw8852c_pwr_on_func()
383 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, in rtw8852c_pwr_off_func()
1728 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_channel_bb()
1734 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_channel_bb()
1935 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_txpwr_ul_tb_offset()
1940 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_txpwr_ul_tb_offset()
2839 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); in rtw8852c_mac_enable_bb_rf()
2840 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); in rtw8852c_mac_enable_bb_rf()
HDefuse.c59 rtw89_write32_mask(rtwdev, R_AX_EFUSE_CTRL_1, B_AX_EF_CELL_SEL_MASK, in rtw89_switch_efuse_bank()
HDdebug.c1397 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_debug_mac_dump_dmac_dbg()
1399 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_debug_mac_dump_dmac_dbg()
1401 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_debug_mac_dump_dmac_dbg()
1404 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in rtw89_debug_mac_dump_dmac_dbg()
2771 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_debug_mac_dbg_port_sel()
2773 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_debug_mac_dbg_port_sel()
3223 rtw89_write32_mask(rtwdev, info->sel_addr, in rtw89_debug_mac_dbg_port_dump()
HDmac.h1101 rtw89_write32_mask(rtwdev, reg, mask, data); in rtw89_write32_port_mask()
1399 rtw89_write32_mask(rtwdev, cr, mask, val); in rtw89_mac_txpwr_write32_mask()
HDrtw8852b_common.c1382 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); in __rtw8852bx_set_txpwr_ul_tb_offset()
1386 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); in __rtw8852bx_set_txpwr_ul_tb_offset()
1985 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); in __rtw8852bx_mac_enable_bb_rf()
HDphy.c4307 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); in rtw89_phy_cfo_set_xcap_reg()
4399 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, in rtw89_dcfo_comp_init()
4858 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, in rtw89_phy_ofdma_power_diff()
4862 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, in rtw89_phy_ofdma_power_diff()
4866 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, in rtw89_phy_ofdma_power_diff()
4870 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, in rtw89_phy_ofdma_power_diff()
6765 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); in rtw89_phy_tssi_ctrl_set_fast_mode_cfg()
6827 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); in rtw89_phy_tssi_ctrl_set_bandedge_cfg()
6831 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); in rtw89_phy_tssi_ctrl_set_bandedge_cfg()
HDrtw8851b.c387 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, in rtw8851b_pwr_on_func()
1792 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); in rtw8851b_set_txpwr_ul_tb_offset()
1796 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); in rtw8851b_set_txpwr_ul_tb_offset()
HDmac80211.c369 rtw89_write32_mask(rtwdev, in rtw89_ops_configure_filter()
375 rtw89_write32_mask(rtwdev, in rtw89_ops_configure_filter()
HDphy.h590 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); in rtw89_phy_write32_mask()
HDrtw8852a.c1428 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); in rtw8852a_set_txpwr_ul_tb_offset()
1431 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); in rtw8852a_set_txpwr_ul_tb_offset()
HDfw.c1516 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_SEL_0XC0_MASK, MAC_DBG_SEL); in rtw89_fw_prog_cnt_dump()
7005 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rx_fltr); in rtw89_hw_scan_start()
7033 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); in rtw89_hw_scan_complete_cb()
HDrtw8851b_rfk.c3137 rtw89_write32_mask(rtwdev, R_AX_PWR_SWING_OTHER_CTRL0, in rtw8851b_by_rate_dpd()
HDcore.h6175 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) in rtw89_write32_mask() function
HDcore.c3416 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); in rtw89_roc_end()