Searched refs:isRegSequence (Results 1 – 24 of 24) sorted by relevance
286 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()332 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()394 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
4379 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) { in getOperandLatency()4717 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()4738 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
1311 let isRegSequence = 1;
72 !MI->isRegSequence() && in canTurnIntoImplicitDef()
244 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()1081 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()1954 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()2139 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
222 if (MI.isRegSequence()) { in getInstrMappingImpl()
1654 assert((MI.isRegSequence() || in getRegSequenceInputs()1657 if (!MI.isRegSequence()) in getRegSequenceInputs()
1337 if (MI.isCopy() || MI.isRegSequence()) { in IsProfitableToHoist()
1800 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence()) in apply()1835 if (TmpMI->isPHI() || TmpMI->isRegSequence()) { in apply()
1860 if (mi->isRegSequence()) in run()
268 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()687 else if (MI.isRegSequence()) in runOnMachineFunction()771 if (MI->isRegSequence()) in runOnMachineFunction()808 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()931 if (Inst->isCopy() || Inst->isRegSequence()) { in analyzeVGPRToSGPRCopy()
661 if (!Def || !Def->isRegSequence()) in getRegSeqInit()774 if (UseMI->isRegSequence()) { in foldOperand()1503 if (InstToErase && InstToErase->isRegSequence() && in tryFoldFoldableCopy()1775 assert(MI.isRegSequence()); in tryFoldRegSequence()2050 if (!I->isCopy() && !I->isRegSequence()) in tryFoldLoad()2205 if (MI.isRegSequence() && tryFoldRegSequence(MI)) { in runOnMachineFunction()
3765 if (MI.isRegSequence()) { in getInstrMapping()
9299 assert(MI.isRegSequence()); in getRegSequenceSubReg()
144 FLAG(isRegSequence) in EmitInstrDocs()
1278 if (Inst.isRegSequence) in emitRecord()
279 bool isRegSequence : 1; variable
462 isRegSequence = R->getValueAsBit("isRegSequence"); in CodeGenInstruction()
662 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)1418 bool isRegSequence() const {
465 if ((DstInst->isRegSequence() || DstInst->isCopy())) { in adjustSchedDependency()
935 bool Skip = MI.isCopy() || MI.isRegSequence(); in collectInBlock()
1949 if (MI.isRegSequence()) { in evaluate()
32502 let isRegSequence = 1;
664 bit isRegSequence = false; // Is this instruction a kind of reg sequence?