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Searched refs:getRegClassName (Results 1 – 25 of 31) sorted by relevance

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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDGCNRewritePartialRegUses.cpp233 << TRI->getRegClassName(SubRegRC) in getRegClassWithShiftedSubregs()
420 << ':' << TRI->getRegClassName(RC) << '\n'); in rewriteReg()
438 LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << " & " in rewriteReg()
439 << TRI->getRegClassName(OpDescRC) << " = "); in rewriteReg()
448 LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << '\n'); in rewriteReg()
459 << TRI->getRegClassName(RC) << " -> " in rewriteReg()
461 << TRI->getRegClassName(NewRC) << '\n'); in rewriteReg()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDRegisterBank.cpp95 OS << LS << TRI->getRegClassName(&RC); in print()
HDLiveStacks.cpp81 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
HDRegAllocBase.cpp107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
HDRegisterClassInfo.cpp189 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
HDVirtRegMap.cpp152 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
160 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
HDExecutionDomainFix.cpp423 << TRI->getRegClassName(RC) << " **********\n"); in runOnMachineFunction()
HDRegisterScavenging.cpp276 TRI->getRegClassName(&RC) + in spill()
HDLiveRangeEdit.cpp504 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n'; in calculateRegClassAndHint()
HDMachineVerifier.cpp2515 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2600 << TRI->getRegClassName( in visitMachineOperand()
2613 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2619 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2642 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
2643 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
HDTargetRegisterInfo.cpp176 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
HDAggressiveAntiDepBreaker.cpp529 LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); in GetRenameRegisters()
HDRegAllocPBQP.cpp895 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); in PrintNodeInfo()
HDRegAllocFast.cpp898 << " in class " << TRI->getRegClassName(&RC) in allocVirtReg()
HDInlineSpiller.cpp1294 << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) in spill()
HDRegisterCoalescer.cpp2087 << TRI->getRegClassName(CP.getNewRC()) << " with "; in joinCopy()
4266 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); in runOnMachineFunction()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDTargetRegisterInfo.h824 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
825 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
HDAMDGPUDisassembler.h122 const char* getRegClassName(unsigned RegClassID) const;
HDAMDGPUDisassembler.cpp1159 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
1161 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1184 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
1232 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonRegisterInfo.cpp111 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
HDHexagonBitTracker.cpp108 << TRI.getRegClassName(&RC) << '\n'; in mask()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/MC/
HDMCRegisterInfo.h456 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
HDMIRParser.cpp711 TRI->getRegClassName(Info.D.RC) + "' for virtual register " + in setupRegisterInfo()
HDMIParser.cpp279 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC)); in initNames2RegClasses()
1590 Twine(TRI.getRegClassName(RegInfo.D.RC))); in parseRegisterClassOrBank()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
HDAMDGPUInstPrinter.cpp814 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC) in printRegularOperand()

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