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Searched refs:X86 (Results 1 – 25 of 234) sorted by relevance

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/freebsd-14-stable/contrib/llvm-project/clang/lib/Sema/
HDSemaX86.cpp36 case X86::BI__builtin_ia32_vcvttsd2si32: in CheckBuiltinRoundingOrSAE()
37 case X86::BI__builtin_ia32_vcvttsd2si64: in CheckBuiltinRoundingOrSAE()
38 case X86::BI__builtin_ia32_vcvttsd2usi32: in CheckBuiltinRoundingOrSAE()
39 case X86::BI__builtin_ia32_vcvttsd2usi64: in CheckBuiltinRoundingOrSAE()
40 case X86::BI__builtin_ia32_vcvttss2si32: in CheckBuiltinRoundingOrSAE()
41 case X86::BI__builtin_ia32_vcvttss2si64: in CheckBuiltinRoundingOrSAE()
42 case X86::BI__builtin_ia32_vcvttss2usi32: in CheckBuiltinRoundingOrSAE()
43 case X86::BI__builtin_ia32_vcvttss2usi64: in CheckBuiltinRoundingOrSAE()
44 case X86::BI__builtin_ia32_vcvttsh2si32: in CheckBuiltinRoundingOrSAE()
45 case X86::BI__builtin_ia32_vcvttsh2si64: in CheckBuiltinRoundingOrSAE()
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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
HDX86InstPrinterCommon.cpp33 bool IsCMPCCXADD = X86::isCMPCCXADD(Opc); in printCondCode()
34 bool IsCCMPOrCTEST = X86::isCCMPCC(Opc) || X86::isCTESTCC(Opc); in printCondCode()
139 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
140 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
141 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
142 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
143 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
144 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
145 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
146 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
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HDX86ATTInstPrinter.cpp57 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
58 (STI.hasFeature(X86::Is64Bit))) { in printInst()
67 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
68 STI.hasFeature(X86::Is16Bit)) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrmi: case X86::CMPSDrri: in printVecCompareInstr()
95 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: in printVecCompareInstr()
96 case X86::CMPSSrmi: case X86::CMPSSrri: in printVecCompareInstr()
97 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: in printVecCompareInstr()
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HDX86IntelInstPrinter.cpp46 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
47 STI.hasFeature(X86::Is16Bit)) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrmi: case X86::CMPSDrri: in printVecCompareInstr()
75 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: in printVecCompareInstr()
76 case X86::CMPSSrmi: case X86::CMPSSrri: in printVecCompareInstr()
77 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
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HDX86BaseInfo.h25 namespace X86 {
131 case X86::TEST16i16: in classifyFirstOpcodeInMacroFusion()
132 case X86::TEST16mr: in classifyFirstOpcodeInMacroFusion()
133 case X86::TEST16ri: in classifyFirstOpcodeInMacroFusion()
134 case X86::TEST16rr: in classifyFirstOpcodeInMacroFusion()
135 case X86::TEST32i32: in classifyFirstOpcodeInMacroFusion()
136 case X86::TEST32mr: in classifyFirstOpcodeInMacroFusion()
137 case X86::TEST32ri: in classifyFirstOpcodeInMacroFusion()
138 case X86::TEST32rr: in classifyFirstOpcodeInMacroFusion()
139 case X86::TEST64i32: in classifyFirstOpcodeInMacroFusion()
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HDX86MCTargetDesc.cpp74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && Base.getReg() == 0 && in is16BitMemOperand()
94 return isMemOperand(MI, Op, X86::GR16RegClassID); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand()
100 if (Base.isReg() && Base.getReg() == X86::EIP) { in is32BitMemOperand()
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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86FixupInstTuning.cpp228 case X86::VPERMILPDri: in processInstruction()
229 return ProcessVPERMILPDri(X86::VSHUFPDrri); in processInstruction()
230 case X86::VPERMILPDYri: in processInstruction()
231 return ProcessVPERMILPDri(X86::VSHUFPDYrri); in processInstruction()
232 case X86::VPERMILPDZ128ri: in processInstruction()
233 return ProcessVPERMILPDri(X86::VSHUFPDZ128rri); in processInstruction()
234 case X86::VPERMILPDZ256ri: in processInstruction()
235 return ProcessVPERMILPDri(X86::VSHUFPDZ256rri); in processInstruction()
236 case X86::VPERMILPDZri: in processInstruction()
237 return ProcessVPERMILPDri(X86::VSHUFPDZrri); in processInstruction()
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HDX86InstrInfo.cpp86 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
87 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
88 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
89 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
90 X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)), in X86InstrInfo()
109 case X86::GR8RegClassID: in getRegClass()
110 return &X86::GR8_NOREX2RegClass; in getRegClass()
111 case X86::GR16RegClassID: in getRegClass()
112 return &X86::GR16_NOREX2RegClass; in getRegClass()
113 case X86::GR32RegClassID: in getRegClass()
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HDX86FloatingPoint.cpp130 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
131 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
132 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
204 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
240 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
250 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
294 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
295 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
317 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
318 return Reg - X86::FP0; in getFPReg()
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HDX86FixupVectorConstants.cpp359 assert(MI.getNumOperands() >= (OperandNo + X86::AddrNumOperands) && in processInstruction()
361 if (auto *C = X86::getConstantFromPool(MI, OperandNo)) { in processInstruction()
373 MI.getOperand(OperandNo + X86::AddrDisp).setIndex(NewCPI); in processInstruction()
393 case X86::MOVAPDrm: in processInstruction()
394 case X86::MOVAPSrm: in processInstruction()
395 case X86::MOVUPDrm: in processInstruction()
396 case X86::MOVUPSrm: in processInstruction()
398 return FixupConstant({{X86::MOVSSrm, 1, 32, rebuildZeroUpperCst}, in processInstruction()
399 {X86::MOVSDrm, 1, 64, rebuildZeroUpperCst}}, in processInstruction()
401 case X86::VMOVAPDrm: in processInstruction()
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HDX86InstrFoldTables.cpp30 { X86::VANDNPDZ128rr, X86::VANDNPSZ128rmb, TB_BCAST_SS },
31 { X86::VANDNPDZ256rr, X86::VANDNPSZ256rmb, TB_BCAST_SS },
32 { X86::VANDNPDZrr, X86::VANDNPSZrmb, TB_BCAST_SS },
33 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rmb, TB_BCAST_SD },
34 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rmb, TB_BCAST_SD },
35 { X86::VANDNPSZrr, X86::VANDNPDZrmb, TB_BCAST_SD },
36 { X86::VANDPDZ128rr, X86::VANDPSZ128rmb, TB_BCAST_SS },
37 { X86::VANDPDZ256rr, X86::VANDPSZ256rmb, TB_BCAST_SS },
38 { X86::VANDPDZrr, X86::VANDPSZrmb, TB_BCAST_SS },
39 { X86::VANDPSZ128rr, X86::VANDPDZ128rmb, TB_BCAST_SD },
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HDX86DomainReassignment.cpp45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
70 return &X86::VK8RegClass; in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
72 return &X86::VK16RegClass; in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
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HDX86AvoidStoreForwardingBlocks.cpp134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
141 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
144 return Opcode == X86::VMOVUPSYrm || Opcode == X86::VMOVAPSYrm || in isYMMLoadOpcode()
145 Opcode == X86::VMOVUPDYrm || Opcode == X86::VMOVAPDYrm || in isYMMLoadOpcode()
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HDX86MCInstLower.cpp335 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32; in getRetOpcode()
374 case X86::TAILJMPr: in convertTailJumpOpcode()
375 Opcode = X86::JMP32r; in convertTailJumpOpcode()
377 case X86::TAILJMPm: in convertTailJumpOpcode()
378 Opcode = X86::JMP32m; in convertTailJumpOpcode()
380 case X86::TAILJMPr64: in convertTailJumpOpcode()
381 Opcode = X86::JMP64r; in convertTailJumpOpcode()
383 case X86::TAILJMPm64: in convertTailJumpOpcode()
384 Opcode = X86::JMP64m; in convertTailJumpOpcode()
386 case X86::TAILJMPr64_REX: in convertTailJumpOpcode()
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HDX86ExpandPseudo.cpp107 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
108 .addReg(X86::RIP) in INITIALIZE_PASS()
114 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
116 .addReg(X86::R11); in INITIALIZE_PASS()
122 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
123 MBB->addLiveIn(X86::EFLAGS); in INITIALIZE_PASS()
128 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC); in INITIALIZE_PASS()
143 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
156 EmitCondJumpTarget(X86::COND_B, FirstTarget); in INITIALIZE_PASS()
163 EmitCondJumpTarget(X86::COND_B, FirstTarget); in INITIALIZE_PASS()
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HDX86RegisterInfo.cpp49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
69 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; in X86RegisterInfo()
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
73 StackPtr = X86::ESP; in X86RegisterInfo()
74 FramePtr = X86::EBP; in X86RegisterInfo()
75 BasePtr = X86::ESI; in X86RegisterInfo()
89 if (!Is64Bit && Idx == X86::sub_8bit) in getSubClassWithSubReg()
90 Idx = X86::sub_8bit_hi; in getSubClassWithSubReg()
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HDX86CompressEVEX.cpp89 if (Reg >= X86::XMM16 && Reg <= X86::XMM31) in usesExtendedRegister()
92 if (Reg >= X86::YMM16 && Reg <= X86::YMM31) in usesExtendedRegister()
121 case X86::VALIGNDZ128rri: in performCustomAdjustments()
122 case X86::VALIGNDZ128rmi: in performCustomAdjustments()
123 case X86::VALIGNQZ128rri: in performCustomAdjustments()
124 case X86::VALIGNQZ128rmi: { in performCustomAdjustments()
125 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
128 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4; in performCustomAdjustments()
133 case X86::VSHUFF32X4Z256rmi: in performCustomAdjustments()
134 case X86::VSHUFF32X4Z256rri: in performCustomAdjustments()
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HDX86FastISel.cpp161 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
219 X86::AddrIndexReg); in addFullAddress()
225 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, in foldX86XALUIntrinsic()
245 X86::CondCode TmpCC; in foldX86XALUIntrinsic()
251 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break; in foldX86XALUIntrinsic()
253 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break; in foldX86XALUIntrinsic()
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
340 Opc = X86::MOV16rm; in X86FastEmitLoad()
343 Opc = X86::MOV32rm; in X86FastEmitLoad()
347 Opc = X86::MOV64rm; in X86FastEmitLoad()
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HDX86InsertWait.cpp60 case X86::FNINIT: in isX87ControlInstruction()
61 case X86::FLDCW16m: in isX87ControlInstruction()
62 case X86::FNSTCW16m: in isX87ControlInstruction()
63 case X86::FNSTSW16r: in isX87ControlInstruction()
64 case X86::FNSTSWm: in isX87ControlInstruction()
65 case X86::FNCLEX: in isX87ControlInstruction()
66 case X86::FLDENVm: in isX87ControlInstruction()
67 case X86::FSTENVm: in isX87ControlInstruction()
68 case X86::FRSTORm: in isX87ControlInstruction()
69 case X86::FSAVEm: in isX87ControlInstruction()
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HDX86TargetTransformInfo.h42 X86::FeatureX86_64,
45 X86::FeatureNOPL,
46 X86::FeatureCX16,
47 X86::FeatureLAHFSAHF64,
50 X86::FeatureSSEUnalignedMem,
53 X86::TuningFast11ByteNOP,
54 X86::TuningFast15ByteNOP,
55 X86::TuningFastBEXTR,
56 X86::TuningFastHorizontalOps,
57 X86::TuningFastLZCNT,
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HDX86SpeculativeLoadHardening.cpp255 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc); in splitEdge()
378 if (MI.getOpcode() == X86::LFENCE) in hasVulnerableLoad()
386 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
415 PS.emplace(MF, &X86::GR64_NOSPRegClass); in runOnMachineFunction()
448 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV64ri32), PS->PoisonReg) in runOnMachineFunction()
461 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::LFENCE)); in runOnMachineFunction()
481 Register PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass); in runOnMachineFunction()
482 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0), in runOnMachineFunction()
486 ZeroI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in runOnMachineFunction()
490 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG), in runOnMachineFunction()
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HDX86FrameLowering.cpp110 return IsLP64 ? X86::SUB64ri32 : X86::SUB32ri; in getSUBriOpcode()
114 return IsLP64 ? X86::ADD64ri32 : X86::ADD32ri; in getADDriOpcode()
118 return IsLP64 ? X86::SUB64rr : X86::SUB32rr; in getSUBrrOpcode()
122 return IsLP64 ? X86::ADD64rr : X86::ADD32rr; in getADDrrOpcode()
126 return IsLP64 ? X86::AND64ri32 : X86::AND32ri; in getANDriOpcode()
130 return IsLP64 ? X86::LEA64r : X86::LEA32r; in getLEArOpcode()
136 return X86::MOV32ri64; in getMOVriOpcode()
138 return X86::MOV64ri32; in getMOVriOpcode()
139 return X86::MOV64ri; in getMOVriOpcode()
141 return X86::MOV32ri; in getMOVriOpcode()
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HDX86FlagsCopyLowering.cpp74 using CondRegArray = std::array<unsigned, X86::LAST_VALID_COND + 1>;
100 const DebugLoc &TestLoc, X86::CondCode Cond);
103 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
136 return X86::isADC(Opc) || X86::isSBB(Opc) || X86::isRCL(Opc) || in isArithmeticOp()
137 X86::isRCR(Opc) || (Opc == X86::SETB_C32r || Opc == X86::SETB_C64r); in isArithmeticOp()
149 assert(X86::getCondFromBranch(SplitI) != X86::COND_INVALID && in splitBlock()
155 assert(X86::getCondFromBranch(PrevI) != X86::COND_INVALID && in splitBlock()
244 MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in getClobberType()
247 if (FlagDef->isDead() && X86::getNFVariant(MI.getOpcode())) in getClobberType()
261 PromoteRC = &X86::GR8RegClass; in runOnMachineFunction()
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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/GISel/
HDX86InstructionSelector.cpp173 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
175 return &X86::GR8RegClass; in getRegClass()
177 return &X86::GR16RegClass; in getRegClass()
179 return &X86::GR32RegClass; in getRegClass()
181 return &X86::GR64RegClass; in getRegClass()
183 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
185 return STI.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass; in getRegClass()
187 return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass; in getRegClass()
189 return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass; in getRegClass()
191 return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass; in getRegClass()
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/freebsd-14-stable/contrib/llvm-project/llvm/lib/TargetParser/
HDHost.cpp724 if (testFeature(X86::FEATURE_MMX)) { in getIntelProcessorTypeAndSubtype()
740 *Type = X86::INTEL_CORE2; in getIntelProcessorTypeAndSubtype()
749 *Type = X86::INTEL_CORE2; in getIntelProcessorTypeAndSubtype()
758 *Type = X86::INTEL_COREI7; in getIntelProcessorTypeAndSubtype()
759 *Subtype = X86::INTEL_COREI7_NEHALEM; in getIntelProcessorTypeAndSubtype()
766 *Type = X86::INTEL_COREI7; in getIntelProcessorTypeAndSubtype()
767 *Subtype = X86::INTEL_COREI7_WESTMERE; in getIntelProcessorTypeAndSubtype()
773 *Type = X86::INTEL_COREI7; in getIntelProcessorTypeAndSubtype()
774 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; in getIntelProcessorTypeAndSubtype()
779 *Type = X86::INTEL_COREI7; in getIntelProcessorTypeAndSubtype()
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