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/freebsd-14-stable/crypto/openssl/crypto/sha/asm/
HDsha256-c64xplus.pl42 ($Xn,$X0,$K)=("B7","B8","B9");
117 || SWAP4 $Xn,$X0
121 || SWAP2 $X0,$X0
138 ADD $X0,$T1,$T1 ; T1 += X[i];
139 || STW $X0,*$Xib++
150 || MV $X0,$X14
151 || SWAP4 $Xn,$X0
152 SWAP2 $X0,$X0
177 ADD $X0,$T1,$T1 ; T1 += X[i];
178 || STW $X0,*$Xib++
[all …]
HDsha1-c64xplus.pl40 ($X0,$X2,$X8,$X13) = ("A26","B26","A27","B27");
137 || LDW *${XPA}++,$X0 ; fetches from X ring buffer are
162 || XOR $X0,$X2,$TX0 ; Xupdate XORs are 1 iteration ahead
163 || LDW *${XPA}++,$X0
193 || XOR $X0,$X2,$TX0
194 || LDW *${XPA}++,$X0
230 || XOR $X0,$X2,$TX0
231 || LDW *${XPA}++,$X0
270 || XOR $X0,$X2,$TX0
271 || LDW *${XPA}++,$X0
/freebsd-14-stable/sys/contrib/libsodium/src/libsodium/crypto_pwhash/scryptsalsa208sha256/sse/
HDpwhash_scryptsalsa208sha256_sse.c67 ARX(X1, X0, X3, 7) \
68 ARX(X2, X1, X0, 9) \
70 ARX(X0, X3, X2, 18) \
78 ARX(X3, X0, X1, 7) \
79 ARX(X2, X3, X0, 9) \
81 ARX(X0, X1, X2, 18) \
93 __m128i Y0 = X0 = _mm_xor_si128(X0, (in)[0]); \
100 SALSA20_2ROUNDS(out)[0] = X0 = _mm_add_epi32(X0, Y0); \
114 __m128i X0, X1, X2, X3; in blockmix_salsa8() local
118 X0 = Bin[8 * r - 4]; in blockmix_salsa8()
[all …]
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
HDRISCVMCTargetDesc.cpp130 return Reg >= RISCV::X0 && Reg <= RISCV::X31; in isGPR()
134 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg"); in getRegIndex()
139 if (Reg == RISCV::X0) in setGPRState()
153 if (Reg == RISCV::X0) in getGPRState()
242 return Inst.getOperand(0).getReg() == RISCV::X0; in isTerminator()
255 return Inst.getOperand(0).getReg() != RISCV::X0; in isCall()
267 return Inst.getOperand(0).getReg() == RISCV::X0 && in isReturn()
296 return Inst.getOperand(0).getReg() == RISCV::X0 && in isIndirectBranch()
314 return Inst.getOperand(0).getReg() == RISCV::X0; in isBranchImpl()
316 return Inst.getOperand(0).getReg() == RISCV::X0 && in isBranchImpl()
HDRISCVMCCodeEmitter.cpp157 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
260 SrcReg2.id() == RISCV::X0) { in expandLongCondBr()
263 SrcReg1.id() == RISCV::X0) { in expandLongCondBr()
291 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol); in expandLongCondBr()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVInstrInfo.td859 def : InstAlias<"nop", (ADDI X0, X0, 0)>;
886 def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm)>;
889 def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
892 def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>;
897 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;
898 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
899 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
907 (BEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
909 (BNE GPR:$rs, X0, simm13_lsb0:$offset)>;
911 (BGE X0, GPR:$rs, simm13_lsb0:$offset)>;
[all …]
HDRISCVRedundantCopyElimination.cpp81 Cond[2].getReg() == RISCV::X0 && TBB == &MBB) in guaranteesZeroRegInBlock()
84 Cond[2].getReg() == RISCV::X0 && TBB != &MBB) in guaranteesZeroRegInBlock()
125 if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) && in optimizeBlock()
HDRISCVInsertVSETVLI.cpp78 assert(RISCV::X0 == MI.getOperand(1).getReg()); in isVLPreservingConfig()
79 return RISCV::X0 == MI.getOperand(0).getReg(); in isVLPreservingConfig()
167 MI.getOperand(1).getReg() == RISCV::X0 && in isNonZeroLoadImmediate()
967 assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) && in getInfoForVSETVLI()
969 if (AVLReg == RISCV::X0) in getInfoForVSETVLI()
1085 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
1086 .addReg(RISCV::X0, RegState::Kill) in insertVSETVLI()
1103 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
1104 .addReg(RISCV::X0, RegState::Kill) in insertVSETVLI()
1117 .addReg(RISCV::X0, RegState::Define | RegState::Dead) in insertVSETVLI()
[all …]
HDRISCVDeadRegisterDefinitions.cpp97 if (!(RC && RC->contains(RISCV::X0))) { in runOnMachineFunction()
103 MO.setReg(RISCV::X0); in runOnMachineFunction()
HDRISCVAsmPrinter.cpp280 Hint.addOperand(MCOperand::createReg(RISCV::X0)); in emitNTLHint()
281 Hint.addOperand(MCOperand::createReg(RISCV::X0)); in emitNTLHint()
339 OS << RISCVInstPrinter::getRegisterName(RISCV::X0); in PrintAsmOperand()
520 std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
557 if (AddrReg == RISCV::X0) { in LowerKCFI_CHECK()
562 .addReg(RISCV::X0) in LowerKCFI_CHECK()
690 .addReg(RISCV::X0) in EmitHwasanMemaccessSymbols()
698 .addReg(RISCV::X0) in EmitHwasanMemaccessSymbols()
814 .addReg(RISCV::X0) in EmitHwasanMemaccessSymbols()
HDRISCVInstrInfoSFB.td35 // We use GPRNoX0 because c.mv cannot encode X0.
198 (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2,
199 (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>;
202 (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2,
203 (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
HDRISCVInstrInfoC.td709 def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
710 def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
711 def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
712 def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
906 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
922 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
955 def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm),
967 def : CompressPat<(JAL X0, simm12_lsb0:$offset),
969 def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
972 def : CompressPat<(BEQ X0, GPRC:$rs1, simm9_lsb0:$imm),
[all …]
HDRISCVInstrInfoZb.td460 def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
485 def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
489 def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
534 (BSET (XLenVT X0), GPR:$rs2)>;
536 (ADDI (XLenVT (BSET (XLenVT X0), GPR:$rs2)), -1)>;
595 (MAX GPR:$rs1, (XLenVT (SUBW (XLenVT X0), GPR:$rs1)))>;
654 def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACK GPR:$rs, (XLenVT X0))>;
656 def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
674 (SH2ADD (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i))),
677 (SH3ADD (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i))),
[all …]
HDRISCVRegisterInfo.td86 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
162 def GPRX0 : GPRRegisterClass<(add X0)>;
166 def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
168 def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)>;
173 // stack on some microarchitectures. Also remove the reserved registers X0, X2,
564 // Dummy zero register for use in the register pair containing X0 (as X1 is
565 // not read to or written when the X0 register pair is used).
574 def X0_Pair : RISCVRegWithSubRegs<0, X0.AsmName,
575 [X0, DUMMY_REG_PAIR_WITH_X0],
576 X0.AltNames> {
HDRISCVInstrInfoXTHead.td553 … (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i))), 2)>;
555 … (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i))), 3)>;
600 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
602 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
609 (TH_MVNEZ GPR:$a, (XLenVT X0), GPR:$cond)>;
611 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
613 (TH_MVEQZ GPR:$b, (XLenVT X0), GPR:$cond)>;
615 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
871 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
873 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
[all …]
HDRISCVGISel.td119 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty 0))), (SLTU (XLenVT X0), GPR:$rs1)>;
121 (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)))>;
123 (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>;
HDRISCVExpandAtomicPseudoInsts.cpp296 .addReg(RISCV::X0) in doAtomicBinOpExpansion()
384 .addReg(RISCV::X0) in doMaskedAtomicBinOpExpansion()
544 .addReg(RISCV::X0) in expandAtomicMinMaxOp()
683 .addReg(RISCV::X0) in expandAtomicCmpXchg()
716 .addReg(RISCV::X0) in expandAtomicCmpXchg()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td42 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.
43 // However, on windows, in some circumstances, the SRet is passed in X0 or X1
45 // passed in the alternative register (X0 or X1), not X8:
46 // - X0 for non-instance methods.
57 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>,
94 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
95 [X0, X1, X3, X5]>>>,
100 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
146 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
197 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>,
[all …]
HDAArch64CleanupLocalDynamicTLSPass.cpp106 TII->get(TargetOpcode::COPY), AArch64::X0) in replaceTLSBaseAddrCall()
133 .addReg(AArch64::X0); in setRegister()
HDAArch64AsmPrinter.cpp412 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
432 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
455 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
466 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
476 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
569 AddrIndex = AddrReg - AArch64::X0; in LowerKCFI_CHECK()
606 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
812 .addReg(AArch64::X0) in emitHwasanMemaccessSymbols()
824 if (Reg != AArch64::X0) in emitHwasanMemaccessSymbols()
826 .addReg(AArch64::X0) in emitHwasanMemaccessSymbols()
[all …]
HDAArch64CollectLOH.cpp257 static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
259 if (AArch64::X0 <= Reg && Reg <= AArch64::X28) in mapRegToGPRIndex()
260 return Reg - AArch64::X0; in mapRegToGPRIndex()
/freebsd-14-stable/sys/contrib/openzfs/module/icp/algs/skein/
HDskein_block.c89 uint64_t X0, X1, X2, X3; in Skein_256_Process_Block() local
94 Xptr[0] = &X0; in Skein_256_Process_Block()
123 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_256_Process_Block()
145 X0 += ks[((R) + 1) % 5]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
156 X0 += ks[r + (R) + 0]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
235 ctx->X[0] = X0 ^ w[0]; in Skein_256_Process_Block()
293 uint64_t X0, X1, X2, X3, X4, X5, X6, X7; in Skein_512_Process_Block() local
298 Xptr[0] = &X0; in Skein_512_Process_Block()
337 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_512_Process_Block()
363 X0 += ks[((R) + 1) % 9]; /* inject the key schedule value */\ in Skein_512_Process_Block()
[all …]
/freebsd-14-stable/sys/crypto/skein/
HDskein_block.c81 u64b_t X0,X1,X2,X3; /* local copy of context vars, for speed */ in Skein_256_Process_Block() local
85 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; in Skein_256_Process_Block()
107 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_256_Process_Block()
128 X0 += ks[((R)+1) % 5]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
139 X0 += ks[r+(R)+0]; /* inject the key schedule value */ \ in Skein_256_Process_Block()
213 ctx->X[0] = X0 ^ w[0]; in Skein_256_Process_Block()
266 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ in Skein_512_Process_Block() local
270 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; in Skein_512_Process_Block()
299 X0 = w[0] + ks[0]; /* do the first full key injection */ in Skein_512_Process_Block()
324 X0 += ks[((R)+1) % 9]; /* inject the key schedule value */ \ in Skein_512_Process_Block()
[all …]
/freebsd-14-stable/sys/contrib/libsodium/src/libsodium/crypto_aead/aes256gcm/aesni/
HDaead_aes256gcm_aesni.c62 __m128i X0, X1, X2, X3; in aesni_key256_expand() local
65 X0 = _mm_loadu_si128((const __m128i *) &key[0]); in aesni_key256_expand()
66 rkeys[i++] = X0; in aesni_key256_expand()
73 X3 = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(X3), _mm_castsi128_ps(X0), 0x10)); \ in aesni_key256_expand()
74 X0 = _mm_xor_si128(X0, X3); \ in aesni_key256_expand()
75 X3 = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(X3), _mm_castsi128_ps(X0), 0x8c)); \ in aesni_key256_expand()
76 X0 = _mm_xor_si128(_mm_xor_si128(X0, X3), X1); \ in aesni_key256_expand()
77 rkeys[i++] = X0; \ in aesni_key256_expand()
81 X1 = _mm_shuffle_epi32(_mm_aeskeygenassist_si128(X0, (S)), 0xaa); \ in aesni_key256_expand()
332 __m128i X0 = X0_; \
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
HDRISCVDisassembler.cpp79 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
87 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRX1X5RegisterClass()
187 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRPairRegisterClass()
411 Inst.addOperand(MCOperand::createReg(RISCV::X0)); in decodeRVCInstrRdSImm()
423 Inst.addOperand(MCOperand::createReg(RISCV::X0)); in decodeRVCInstrRdRs1UImm()

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