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Searched refs:SpillToPhysVGPRLane (Results 1 – 4 of 4) sorted by relevance

/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIRegisterInfo.h157 bool SpillToPhysVGPRLane = false) const;
162 bool SpillToPhysVGPRLane = false) const;
175 bool SpillToPhysVGPRLane = false) const;
HDSIMachineFunctionInfo.cpp400 MachineFunction &MF, int FI, bool SpillToPhysVGPRLane, in allocateSGPRSpillToVGPRLane() argument
403 SpillToPhysVGPRLane ? SGPRSpillsToPhysicalVGPRLanes[FI] in allocateSGPRSpillToVGPRLane()
424 unsigned &NumSpillLanes = SpillToPhysVGPRLane ? NumPhysicalVGPRSpillLanes in allocateSGPRSpillToVGPRLane()
430 bool Allocated = SpillToPhysVGPRLane in allocateSGPRSpillToVGPRLane()
HDSIRegisterInfo.cpp1763 bool SpillToPhysVGPRLane) const { in spillSGPR()
1767 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in spillSGPR()
1886 bool SpillToPhysVGPRLane) const { in restoreSGPR()
1890 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in restoreSGPR()
2037 SlotIndexes *Indexes, LiveIntervals *LIS, bool SpillToPhysVGPRLane) const { in eliminateSGPRToVGPRSpillFrameIndex()
2053 return spillSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane); in eliminateSGPRToVGPRSpillFrameIndex()
2068 return restoreSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane); in eliminateSGPRToVGPRSpillFrameIndex()
HDSIMachineFunctionInfo.h728 bool SpillToPhysVGPRLane = false,