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Searched refs:SLOT3 (Results 1 – 21 of 21) sorted by relevance

/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonDepIICScalar.td236 InstrItinData <tc_01d44cb2, [InstrStage<1, [SLOT2, SLOT3]>]>,
237 InstrItinData <tc_01e1be3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
238 InstrItinData <tc_02fe1c65, [InstrStage<1, [SLOT2, SLOT3]>]>,
241 InstrItinData <tc_0a195f2c, [InstrStage<1, [SLOT2, SLOT3]>]>,
244 InstrItinData <tc_0dfac0a7, [InstrStage<1, [SLOT2, SLOT3]>]>,
246 InstrItinData <tc_112d30d6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
248 InstrItinData <tc_1248597c, [InstrStage<1, [SLOT3]>]>,
250 InstrItinData <tc_151bf368, [InstrStage<1, [SLOT2, SLOT3]>]>,
252 InstrItinData <tc_197dce51, [InstrStage<1, [SLOT3]>]>,
254 InstrItinData <tc_1c2c7a4a, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
[all …]
HDHexagonDepIICHVX.td132 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
137 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
142 [InstrStage<1, [SLOT2, SLOT3], 0>,
147 [InstrStage<1, [SLOT2, SLOT3], 0>,
152 [InstrStage<1, [SLOT2, SLOT3], 0>,
157 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
169 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
174 [InstrStage<1, [SLOT2, SLOT3], 0>,
180 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
191 [InstrStage<1, [SLOT2, SLOT3], 0>,
[all …]
HDHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>]>,
32 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
HDHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
34 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
HDHexagonScheduleV71T.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>],
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV67T.td11 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
13 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
14 InstrStage<1, [SLOT2, SLOT3]>],
44 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
HDHexagonScheduleV60.td22 // | SLOT3 | XTYPE ALU32 J CR |
64 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV62.td20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV69.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
HDHexagonScheduleV73.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV71.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV67.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV66.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV68.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonScheduleV65.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
HDHexagonSchedule.td16 def SLOT3 : FuncUnit;
/freebsd-14-stable/sys/dev/sound/pci/
HDvia8233.h128 # define SLOT3(x) (x) macro
HDvia8233.c454 s |= SLOT3(1) | SLOT4(2); in via8233msgd_setformat()
457 s |= SLOT3(1) | SLOT4(1); in via8233msgd_setformat()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCTargetDesc.cpp173 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; } in HexagonGetLastSlot()