Searched refs:RISCVInstrInfo (Results 1 – 18 of 18) sorted by relevance
| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| HD | RISCVInstrInfo.cpp | 77 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) in RISCVInstrInfo() function in RISCVInstrInfo 81 MCInst RISCVInstrInfo::getNop() const { in getNop() 90 Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot() 96 Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot() 131 Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() 137 Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() 169 bool RISCVInstrInfo::isReallyTriviallyReMaterializable( in isReallyTriviallyReMaterializable() 318 void RISCVInstrInfo::copyPhysRegVector( in copyPhysRegVector() 440 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg() 559 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, in storeRegToStackSlot() [all …]
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| HD | RISCV.td | 36 include "RISCVInstrInfo.td" 67 def RISCVInstrInfo : InstrInfo { 81 let InstructionSet = RISCVInstrInfo;
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| HD | RISCVOptWInstrs.cpp | 68 bool removeSExtWInstrs(MachineFunction &MF, const RISCVInstrInfo &TII, 70 bool stripWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII, 72 bool appendWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII, 631 const RISCVInstrInfo &TII, in removeSExtWInstrs() 683 const RISCVInstrInfo &TII, in stripWSuffixes() 710 const RISCVInstrInfo &TII, in appendWSuffixes() 767 const RISCVInstrInfo &TII = *ST.getInstrInfo(); in runOnMachineFunction()
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| HD | RISCVPostRAExpandPseudoInsts.cpp | 31 const RISCVInstrInfo *TII; 53 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| HD | RISCVSubtarget.h | 86 RISCVInstrInfo InstrInfo; 112 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
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| HD | RISCVExpandAtomicPseudoInsts.cpp | 34 const RISCVInstrInfo *TII; 259 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, in doAtomicBinOpExpansion() 300 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, in insertMaskedMerge() 322 static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII, in doMaskedAtomicBinOpExpansion() 427 static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL, in insertSext()
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| HD | RISCVInstrInfo.h | 62 class RISCVInstrInfo : public RISCVGenInstrInfo { 65 explicit RISCVInstrInfo(RISCVSubtarget &STI);
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| HD | RISCVPushPopOptimizer.cpp | 27 const RISCVInstrInfo *TII;
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| HD | RISCVFrameLowering.cpp | 75 const RISCVInstrInfo *TII = STI.getInstrInfo(); in emitSCSPrologue() 135 const RISCVInstrInfo *TII = STI.getInstrInfo(); in emitSCSEpilogue() 530 const RISCVInstrInfo *TII = STI.getInstrInfo(); in emitPrologue() 725 const RISCVInstrInfo *TII = STI.getInstrInfo(); in emitPrologue() 1181 const RISCVInstrInfo &TII) { in estimateFunctionSizeInBytes() 1222 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); in processFunctionBeforeFrameFinalized()
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| HD | RISCVMoveMerger.cpp | 27 const RISCVInstrInfo *TII;
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| HD | RISCVMakeCompressible.cpp | 384 const RISCVInstrInfo &TII = *STI.getInstrInfo(); in runOnMachineFunction()
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| HD | RISCVExpandPseudoInsts.cpp | 34 const RISCVInstrInfo *TII; 412 const RISCVInstrInfo *TII;
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| HD | RISCVRegisterInfo.cpp | 186 const RISCVInstrInfo *TII = ST.getInstrInfo(); in adjustReg()
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| HD | RISCVInstrInfo.td | 1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===//
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| HD | RISCVISelLowering.cpp | 18328 const RISCVInstrInfo &TII = *Subtarget.getInstrInfo(); in EmitLoweredCascadedSelect() 18471 const RISCVInstrInfo &TII = *Subtarget.getInstrInfo(); in emitSelectPseudo() 18701 const RISCVInstrInfo &TII = *Subtarget.getInstrInfo(); in emitFROUND()
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| HD | RISCVInstrInfoVPseudos.td | 522 // RISCVInstrInfo.h.
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| HD | RISCVInstructionSelector.cpp | 119 const RISCVInstrInfo &TII;
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| /freebsd-14-stable/lib/clang/libllvm/ |
| HD | Makefile | 1577 SRCS_MIN+= Target/RISCV/RISCVInstrInfo.cpp
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