1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 /* Base class for all Synopsys DesignWare PCI/PCIe drivers */
30
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/devmap.h>
36 #include <sys/proc.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43
44 #include <machine/bus.h>
45 #include <machine/intr.h>
46 #include <machine/resource.h>
47
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/ofw/ofw_pci.h>
51 #include <dev/ofw/ofwpci.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pcib_private.h>
55 #include <dev/pci/pci_dw.h>
56
57 #include "pcib_if.h"
58 #include "pci_dw_if.h"
59
60 #ifdef DEBUG
61 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
62 #else
63 #define debugf(fmt, args...)
64 #endif
65
66 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val)
67 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val)
68 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val)
69 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg)
70 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg)
71 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg)
72
73 #define IATU_UR_WR4(sc, reg, val) \
74 bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val))
75 #define IATU_UR_RD4(sc, reg) \
76 bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg))
77
78 #define PCI_BUS_SHIFT 20
79 #define PCI_SLOT_SHIFT 15
80 #define PCI_FUNC_SHIFT 12
81 #define PCI_BUS_MASK 0xFF
82 #define PCI_SLOT_MASK 0x1F
83 #define PCI_FUNC_MASK 0x07
84 #define PCI_REG_MASK 0xFFF
85
86 #define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24)
87 #define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19)
88 #define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16)
89
90 static uint32_t
pci_dw_dbi_read(device_t dev,u_int reg,int width)91 pci_dw_dbi_read(device_t dev, u_int reg, int width)
92 {
93 struct pci_dw_softc *sc;
94
95 sc = device_get_softc(dev);
96 MPASS(sc->dbi_res != NULL);
97
98 switch (width) {
99 case 4:
100 return (bus_read_4(sc->dbi_res, reg));
101 case 2:
102 return (bus_read_2(sc->dbi_res, reg));
103 case 1:
104 return (bus_read_1(sc->dbi_res, reg));
105 default:
106 device_printf(sc->dev, "Unsupported width: %d\n", width);
107 return (0xFFFFFFFF);
108 }
109 }
110
111 static void
pci_dw_dbi_write(device_t dev,u_int reg,uint32_t val,int width)112 pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width)
113 {
114 struct pci_dw_softc *sc;
115
116 sc = device_get_softc(dev);
117 MPASS(sc->dbi_res != NULL);
118
119 switch (width) {
120 case 4:
121 bus_write_4(sc->dbi_res, reg, val);
122 break;
123 case 2:
124 bus_write_2(sc->dbi_res, reg, val);
125 break;
126 case 1:
127 bus_write_1(sc->dbi_res, reg, val);
128 break;
129 default:
130 device_printf(sc->dev, "Unsupported width: %d\n", width);
131 break;
132 }
133 }
134
135 static void
pci_dw_dbi_protect(struct pci_dw_softc * sc,bool protect)136 pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect)
137 {
138 uint32_t reg;
139
140 reg = DBI_RD4(sc, DW_MISC_CONTROL_1);
141 if (protect)
142 reg &= ~DBI_RO_WR_EN;
143 else
144 reg |= DBI_RO_WR_EN;
145 DBI_WR4(sc, DW_MISC_CONTROL_1, reg);
146 }
147
148 static bool
pci_dw_check_dev(struct pci_dw_softc * sc,u_int bus,u_int slot,u_int func,u_int reg)149 pci_dw_check_dev(struct pci_dw_softc *sc, u_int bus, u_int slot, u_int func,
150 u_int reg)
151 {
152 bool status;
153 int rv;
154
155 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX ||
156 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
157 return (false);
158
159 /* link is needed for access to all non-root busses */
160 if (bus != sc->root_bus) {
161 rv = PCI_DW_GET_LINK(sc->dev, &status);
162 if (rv != 0 || !status)
163 return (false);
164 return (true);
165 }
166
167 /* we have only 1 device with 1 function root port */
168 if (slot > 0 || func > 0)
169 return (false);
170 return (true);
171 }
172
173 static bool
pci_dw_detect_atu_unroll(struct pci_dw_softc * sc)174 pci_dw_detect_atu_unroll(struct pci_dw_softc *sc)
175 {
176 return (DBI_RD4(sc, DW_IATU_VIEWPORT) == 0xFFFFFFFFU);
177 }
178
179 static int
pci_dw_detect_out_atu_regions_unroll(struct pci_dw_softc * sc)180 pci_dw_detect_out_atu_regions_unroll(struct pci_dw_softc *sc)
181 {
182 int num_regions, i;
183 uint32_t reg;
184
185 num_regions = sc->iatu_ur_size / DW_IATU_UR_STEP;
186
187 for (i = 0; i < num_regions; ++i) {
188 IATU_UR_WR4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR),
189 0x12340000);
190 reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR));
191 if (reg != 0x12340000)
192 break;
193 }
194
195 sc->num_out_regions = i;
196
197 return (0);
198 }
199
200 static int
pci_dw_detect_out_atu_regions_legacy(struct pci_dw_softc * sc)201 pci_dw_detect_out_atu_regions_legacy(struct pci_dw_softc *sc)
202 {
203 int num_viewports, i;
204 uint32_t reg;
205
206 /* Find out how many viewports there are in total */
207 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(~0U));
208 reg = DBI_RD4(sc, DW_IATU_VIEWPORT);
209 if (reg > IATU_REGION_INDEX(~0U)) {
210 device_printf(sc->dev,
211 "Cannot detect number of output iATU regions; read %#x\n",
212 reg);
213 return (ENXIO);
214 }
215
216 num_viewports = reg + 1;
217
218 /*
219 * Find out how many of them are outbound by seeing whether a dummy
220 * page-aligned address sticks.
221 */
222 for (i = 0; i < num_viewports; ++i) {
223 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(i));
224 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, 0x12340000);
225 reg = DBI_RD4(sc, DW_IATU_LWR_TARGET_ADDR);
226 if (reg != 0x12340000)
227 break;
228 }
229
230 sc->num_out_regions = i;
231
232 return (0);
233 }
234
235 static int
pci_dw_detect_out_atu_regions(struct pci_dw_softc * sc)236 pci_dw_detect_out_atu_regions(struct pci_dw_softc *sc)
237 {
238 if (sc->iatu_ur_res)
239 return (pci_dw_detect_out_atu_regions_unroll(sc));
240 else
241 return (pci_dw_detect_out_atu_regions_legacy(sc));
242 }
243
244 static int
pci_dw_map_out_atu_unroll(struct pci_dw_softc * sc,int idx,int type,uint64_t pa,uint64_t pci_addr,uint32_t size)245 pci_dw_map_out_atu_unroll(struct pci_dw_softc *sc, int idx, int type,
246 uint64_t pa, uint64_t pci_addr, uint32_t size)
247 {
248 uint32_t reg;
249 int i;
250
251 if (size == 0)
252 return (0);
253
254 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_BASE_ADDR),
255 pa & 0xFFFFFFFF);
256 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_BASE_ADDR),
257 (pa >> 32) & 0xFFFFFFFF);
258 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LIMIT_ADDR),
259 (pa + size - 1) & 0xFFFFFFFF);
260 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_TARGET_ADDR),
261 pci_addr & 0xFFFFFFFF);
262 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_TARGET_ADDR),
263 (pci_addr >> 32) & 0xFFFFFFFF);
264 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, CTRL1),
265 IATU_CTRL1_TYPE(type));
266 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, CTRL2),
267 IATU_CTRL2_REGION_EN);
268
269 /* Wait until setup becomes valid */
270 for (i = 10; i > 0; i--) {
271 reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(idx, CTRL2));
272 if (reg & IATU_CTRL2_REGION_EN)
273 return (0);
274 DELAY(5);
275 }
276
277 device_printf(sc->dev,
278 "Cannot map outbound region %d in unroll mode iATU\n", idx);
279 return (ETIMEDOUT);
280 }
281
282 static int
pci_dw_map_out_atu_legacy(struct pci_dw_softc * sc,int idx,int type,uint64_t pa,uint64_t pci_addr,uint32_t size)283 pci_dw_map_out_atu_legacy(struct pci_dw_softc *sc, int idx, int type,
284 uint64_t pa, uint64_t pci_addr, uint32_t size)
285 {
286 uint32_t reg;
287 int i;
288
289 if (size == 0)
290 return (0);
291
292 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(idx));
293 DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF);
294 DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF);
295 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF);
296 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF);
297 DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF);
298 DBI_WR4(sc, DW_IATU_CTRL1, IATU_CTRL1_TYPE(type));
299 DBI_WR4(sc, DW_IATU_CTRL2, IATU_CTRL2_REGION_EN);
300
301 /* Wait until setup becomes valid */
302 for (i = 10; i > 0; i--) {
303 reg = DBI_RD4(sc, DW_IATU_CTRL2);
304 if (reg & IATU_CTRL2_REGION_EN)
305 return (0);
306 DELAY(5);
307 }
308
309 device_printf(sc->dev,
310 "Cannot map outbound region %d in legacy mode iATU\n", idx);
311 return (ETIMEDOUT);
312 }
313
314 /* Map one outbound ATU region */
315 static int
pci_dw_map_out_atu(struct pci_dw_softc * sc,int idx,int type,uint64_t pa,uint64_t pci_addr,uint32_t size)316 pci_dw_map_out_atu(struct pci_dw_softc *sc, int idx, int type,
317 uint64_t pa, uint64_t pci_addr, uint32_t size)
318 {
319 if (sc->iatu_ur_res)
320 return (pci_dw_map_out_atu_unroll(sc, idx, type, pa,
321 pci_addr, size));
322 else
323 return (pci_dw_map_out_atu_legacy(sc, idx, type, pa,
324 pci_addr, size));
325 }
326
327 static int
pci_dw_setup_hw(struct pci_dw_softc * sc)328 pci_dw_setup_hw(struct pci_dw_softc *sc)
329 {
330 uint32_t reg;
331 int rv, i;
332
333 pci_dw_dbi_protect(sc, false);
334
335 /* Setup config registers */
336 DBI_WR1(sc, PCIR_CLASS, PCIC_BRIDGE);
337 DBI_WR1(sc, PCIR_SUBCLASS, PCIS_BRIDGE_PCI);
338 DBI_WR4(sc, PCIR_BAR(0), 4);
339 DBI_WR4(sc, PCIR_BAR(1), 0);
340 DBI_WR1(sc, PCIR_INTPIN, 1);
341 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus);
342 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus);
343 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end);
344 DBI_WR2(sc, PCIR_COMMAND,
345 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN |
346 PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN);
347 pci_dw_dbi_protect(sc, true);
348
349 /* Setup outbound memory windows */
350 for (i = 0; i < min(sc->num_mem_ranges, sc->num_out_regions - 1); ++i) {
351 rv = pci_dw_map_out_atu(sc, i + 1, IATU_CTRL1_TYPE_MEM,
352 sc->mem_ranges[i].host, sc->mem_ranges[i].pci,
353 sc->mem_ranges[i].size);
354 if (rv != 0)
355 return (rv);
356 }
357
358 /* If we have enough regions ... */
359 if (sc->num_mem_ranges + 1 < sc->num_out_regions &&
360 sc->io_range.size != 0) {
361 /* Setup outbound I/O window */
362 rv = pci_dw_map_out_atu(sc, sc->num_mem_ranges + 1,
363 IATU_CTRL1_TYPE_IO, sc->io_range.host, sc->io_range.pci,
364 sc->io_range.size);
365 if (rv != 0)
366 return (rv);
367 }
368
369 /* Adjust number of lanes */
370 reg = DBI_RD4(sc, DW_PORT_LINK_CTRL);
371 reg &= ~PORT_LINK_CAPABLE(~0);
372 switch (sc->num_lanes) {
373 case 1:
374 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_1);
375 break;
376 case 2:
377 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_2);
378 break;
379 case 4:
380 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_4);
381 break;
382 case 8:
383 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_8);
384 break;
385 case 16:
386 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_16);
387 break;
388 case 32:
389 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_32);
390 break;
391 default:
392 device_printf(sc->dev,
393 "'num-lanes' property have invalid value: %d\n",
394 sc->num_lanes);
395 return (EINVAL);
396 }
397 DBI_WR4(sc, DW_PORT_LINK_CTRL, reg);
398
399 /* And link width */
400 reg = DBI_RD4(sc, DW_GEN2_CTRL);
401 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0);
402 switch (sc->num_lanes) {
403 case 1:
404 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_1);
405 break;
406 case 2:
407 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_2);
408 break;
409 case 4:
410 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_4);
411 break;
412 case 8:
413 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_8);
414 break;
415 case 16:
416 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_16);
417 break;
418 case 32:
419 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_32);
420 break;
421 }
422 DBI_WR4(sc, DW_GEN2_CTRL, reg);
423
424 reg = DBI_RD4(sc, DW_GEN2_CTRL);
425 reg |= DIRECT_SPEED_CHANGE;
426 DBI_WR4(sc, DW_GEN2_CTRL, reg);
427
428 return (0);
429 }
430
431 static int
pci_dw_decode_ranges(struct pci_dw_softc * sc,struct ofw_pci_range * ranges,int nranges)432 pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges,
433 int nranges)
434 {
435 int i, nmem, rv;
436
437 nmem = 0;
438 for (i = 0; i < nranges; i++) {
439 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
440 OFW_PCI_PHYS_HI_SPACE_MEM32)
441 ++nmem;
442 }
443
444 sc->mem_ranges = malloc(nmem * sizeof(*sc->mem_ranges), M_DEVBUF,
445 M_WAITOK);
446 sc->num_mem_ranges = nmem;
447
448 nmem = 0;
449 for (i = 0; i < nranges; i++) {
450 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
451 OFW_PCI_PHYS_HI_SPACE_IO) {
452 if (sc->io_range.size != 0) {
453 device_printf(sc->dev,
454 "Duplicated IO range found in DT\n");
455 rv = ENXIO;
456 goto out;
457 }
458
459 sc->io_range = ranges[i];
460 if (sc->io_range.size > UINT32_MAX) {
461 device_printf(sc->dev,
462 "ATU IO window size is too large. "
463 "Up to 4GB windows are supported, "
464 "trimming window size to 4GB\n");
465 sc->io_range.size = UINT32_MAX;
466 }
467 }
468 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
469 OFW_PCI_PHYS_HI_SPACE_MEM32) {
470 MPASS(nmem < sc->num_mem_ranges);
471 sc->mem_ranges[nmem] = ranges[i];
472 if (sc->mem_ranges[nmem].size > UINT32_MAX) {
473 device_printf(sc->dev,
474 "ATU MEM window size is too large. "
475 "Up to 4GB windows are supported, "
476 "trimming window size to 4GB\n");
477 sc->mem_ranges[nmem].size = UINT32_MAX;
478 }
479 ++nmem;
480 }
481 }
482
483 MPASS(nmem == sc->num_mem_ranges);
484
485 if (nmem == 0) {
486 device_printf(sc->dev,
487 "Missing required memory range in DT\n");
488 return (ENXIO);
489 }
490
491 return (0);
492
493 out:
494 free(sc->mem_ranges, M_DEVBUF);
495 return (rv);
496 }
497
498 /*-----------------------------------------------------------------------------
499 *
500 * P C I B I N T E R F A C E
501 */
502
503 static uint32_t
pci_dw_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)504 pci_dw_read_config(device_t dev, u_int bus, u_int slot,
505 u_int func, u_int reg, int bytes)
506 {
507 struct pci_dw_softc *sc;
508 struct resource *res;
509 uint32_t data;
510 uint64_t addr;
511 int type, rv;
512
513 sc = device_get_softc(dev);
514
515 if (!pci_dw_check_dev(sc, bus, slot, func, reg))
516 return (0xFFFFFFFFU);
517
518 if (bus == sc->root_bus) {
519 res = (sc->dbi_res);
520 } else {
521 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) |
522 IATU_CFG_FUNC(func);
523 if (bus == sc->sub_bus)
524 type = IATU_CTRL1_TYPE_CFG0;
525 else
526 type = IATU_CTRL1_TYPE_CFG1;
527 rv = pci_dw_map_out_atu(sc, 0, type,
528 sc->cfg_pa, addr, sc->cfg_size);
529 if (rv != 0)
530 return (0xFFFFFFFFU);
531 res = sc->cfg_res;
532 }
533
534 switch (bytes) {
535 case 1:
536 data = bus_read_1(res, reg);
537 break;
538 case 2:
539 data = bus_read_2(res, reg);
540 break;
541 case 4:
542 data = bus_read_4(res, reg);
543 break;
544 default:
545 data = 0xFFFFFFFFU;
546 }
547
548 return (data);
549
550 }
551
552 static void
pci_dw_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)553 pci_dw_write_config(device_t dev, u_int bus, u_int slot,
554 u_int func, u_int reg, uint32_t val, int bytes)
555 {
556 struct pci_dw_softc *sc;
557 struct resource *res;
558 uint64_t addr;
559 int type, rv;
560
561 sc = device_get_softc(dev);
562 if (!pci_dw_check_dev(sc, bus, slot, func, reg))
563 return;
564
565 if (bus == sc->root_bus) {
566 res = (sc->dbi_res);
567 } else {
568 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) |
569 IATU_CFG_FUNC(func);
570 if (bus == sc->sub_bus)
571 type = IATU_CTRL1_TYPE_CFG0;
572 else
573 type = IATU_CTRL1_TYPE_CFG1;
574 rv = pci_dw_map_out_atu(sc, 0, type,
575 sc->cfg_pa, addr, sc->cfg_size);
576 if (rv != 0)
577 return ;
578 res = sc->cfg_res;
579 }
580
581 switch (bytes) {
582 case 1:
583 bus_write_1(res, reg, val);
584 break;
585 case 2:
586 bus_write_2(res, reg, val);
587 break;
588 case 4:
589 bus_write_4(res, reg, val);
590 break;
591 default:
592 break;
593 }
594 }
595
596 static int
pci_dw_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)597 pci_dw_alloc_msi(device_t pci, device_t child, int count,
598 int maxcount, int *irqs)
599 {
600 phandle_t msi_parent;
601 int rv;
602
603 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
604 &msi_parent, NULL);
605 if (rv != 0)
606 return (rv);
607
608 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
609 irqs));
610 }
611
612 static int
pci_dw_release_msi(device_t pci,device_t child,int count,int * irqs)613 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs)
614 {
615 phandle_t msi_parent;
616 int rv;
617
618 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
619 &msi_parent, NULL);
620 if (rv != 0)
621 return (rv);
622 return (intr_release_msi(pci, child, msi_parent, count, irqs));
623 }
624
625 static int
pci_dw_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)626 pci_dw_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
627 uint32_t *data)
628 {
629 phandle_t msi_parent;
630 int rv;
631
632 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
633 &msi_parent, NULL);
634 if (rv != 0)
635 return (rv);
636
637 return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
638 }
639
640 static int
pci_dw_alloc_msix(device_t pci,device_t child,int * irq)641 pci_dw_alloc_msix(device_t pci, device_t child, int *irq)
642 {
643 phandle_t msi_parent;
644 int rv;
645
646 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
647 &msi_parent, NULL);
648 if (rv != 0)
649 return (rv);
650 return (intr_alloc_msix(pci, child, msi_parent, irq));
651 }
652
653 static int
pci_dw_release_msix(device_t pci,device_t child,int irq)654 pci_dw_release_msix(device_t pci, device_t child, int irq)
655 {
656 phandle_t msi_parent;
657 int rv;
658
659 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
660 &msi_parent, NULL);
661 if (rv != 0)
662 return (rv);
663 return (intr_release_msix(pci, child, msi_parent, irq));
664 }
665
666 static int
pci_dw_get_id(device_t pci,device_t child,enum pci_id_type type,uintptr_t * id)667 pci_dw_get_id(device_t pci, device_t child, enum pci_id_type type,
668 uintptr_t *id)
669 {
670 phandle_t node;
671 int rv;
672 uint32_t rid;
673 uint16_t pci_rid;
674
675 if (type != PCI_ID_MSI)
676 return (pcib_get_id(pci, child, type, id));
677
678 node = ofw_bus_get_node(pci);
679 pci_rid = pci_get_rid(child);
680
681 rv = ofw_bus_msimap(node, pci_rid, NULL, &rid);
682 if (rv != 0)
683 return (rv);
684 *id = rid;
685
686 return (0);
687 }
688
689 /*-----------------------------------------------------------------------------
690 *
691 * B U S / D E V I C E I N T E R F A C E
692 */
693 static bus_dma_tag_t
pci_dw_get_dma_tag(device_t dev,device_t child)694 pci_dw_get_dma_tag(device_t dev, device_t child)
695 {
696 struct pci_dw_softc *sc;
697
698 sc = device_get_softc(dev);
699 return (sc->dmat);
700 }
701
702 int
pci_dw_init(device_t dev)703 pci_dw_init(device_t dev)
704 {
705 struct pci_dw_softc *sc;
706 int rv, rid;
707 bool unroll_mode;
708
709 sc = device_get_softc(dev);
710 sc->dev = dev;
711 sc->node = ofw_bus_get_node(dev);
712
713 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF);
714
715 /* XXXn Should not be this configurable ? */
716 sc->bus_start = 0;
717 sc->bus_end = 255;
718 sc->root_bus = 0;
719 sc->sub_bus = 1;
720
721 /* Read FDT properties */
722 if (!sc->coherent)
723 sc->coherent = OF_hasprop(sc->node, "dma-coherent");
724
725 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes,
726 sizeof(sc->num_lanes));
727 if (rv != sizeof(sc->num_lanes))
728 sc->num_lanes = 1;
729 if (sc->num_lanes != 1 && sc->num_lanes != 2 &&
730 sc->num_lanes != 4 && sc->num_lanes != 8) {
731 device_printf(dev,
732 "invalid number of lanes: %d\n",sc->num_lanes);
733 sc->num_lanes = 0;
734 rv = ENXIO;
735 goto out;
736 }
737
738 rid = 0;
739 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid);
740 if (rv != 0) {
741 device_printf(dev, "Cannot get config space memory\n");
742 rv = ENXIO;
743 goto out;
744 }
745 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
746 RF_ACTIVE);
747 if (sc->cfg_res == NULL) {
748 device_printf(dev, "Cannot allocate config space(rid: %d)\n",
749 rid);
750 rv = ENXIO;
751 goto out;
752 }
753
754 /* Fill up config region related variables */
755 sc->cfg_size = rman_get_size(sc->cfg_res);
756 sc->cfg_pa = rman_get_start(sc->cfg_res) ;
757
758 if (bootverbose)
759 device_printf(dev, "Bus is%s cache-coherent\n",
760 sc->coherent ? "" : " not");
761 rv = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
762 1, 0, /* alignment, bounds */
763 BUS_SPACE_MAXADDR, /* lowaddr */
764 BUS_SPACE_MAXADDR, /* highaddr */
765 NULL, NULL, /* filter, filterarg */
766 BUS_SPACE_MAXSIZE, /* maxsize */
767 BUS_SPACE_UNRESTRICTED, /* nsegments */
768 BUS_SPACE_MAXSIZE, /* maxsegsize */
769 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
770 NULL, NULL, /* lockfunc, lockarg */
771 &sc->dmat);
772 if (rv != 0)
773 goto out;
774
775 rv = ofw_pcib_init(dev);
776 if (rv != 0)
777 goto out;
778 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range,
779 sc->ofw_pci.sc_nrange);
780 if (rv != 0)
781 goto out;
782
783 unroll_mode = pci_dw_detect_atu_unroll(sc);
784 if (bootverbose)
785 device_printf(dev, "Using iATU %s mode\n",
786 unroll_mode ? "unroll" : "legacy");
787 if (unroll_mode) {
788 rid = 0;
789 rv = ofw_bus_find_string_index(sc->node, "reg-names", "atu", &rid);
790 if (rv == 0) {
791 sc->iatu_ur_res = bus_alloc_resource_any(dev,
792 SYS_RES_MEMORY, &rid, RF_ACTIVE);
793 if (sc->iatu_ur_res == NULL) {
794 device_printf(dev,
795 "Cannot allocate iATU space (rid: %d)\n",
796 rid);
797 rv = ENXIO;
798 goto out;
799 }
800 sc->iatu_ur_offset = 0;
801 sc->iatu_ur_size = rman_get_size(sc->iatu_ur_res);
802 } else if (rv == ENOENT) {
803 sc->iatu_ur_res = sc->dbi_res;
804 sc->iatu_ur_offset = DW_DEFAULT_IATU_UR_DBI_OFFSET;
805 sc->iatu_ur_size = DW_DEFAULT_IATU_UR_DBI_SIZE;
806 } else {
807 device_printf(dev, "Cannot get iATU space memory\n");
808 rv = ENXIO;
809 goto out;
810 }
811 }
812
813 rv = pci_dw_detect_out_atu_regions(sc);
814 if (rv != 0)
815 goto out;
816
817 if (bootverbose)
818 device_printf(sc->dev, "Detected outbound iATU regions: %d\n",
819 sc->num_out_regions);
820
821 rv = pci_dw_setup_hw(sc);
822 if (rv != 0)
823 goto out;
824
825 device_add_child(dev, "pci", -1);
826
827 return (0);
828 out:
829 /* XXX Cleanup */
830 return (rv);
831 }
832
833 static device_method_t pci_dw_methods[] = {
834 /* Bus interface */
835 DEVMETHOD(bus_get_dma_tag, pci_dw_get_dma_tag),
836
837 /* pcib interface */
838 DEVMETHOD(pcib_read_config, pci_dw_read_config),
839 DEVMETHOD(pcib_write_config, pci_dw_write_config),
840 DEVMETHOD(pcib_alloc_msi, pci_dw_alloc_msi),
841 DEVMETHOD(pcib_release_msi, pci_dw_release_msi),
842 DEVMETHOD(pcib_alloc_msix, pci_dw_alloc_msix),
843 DEVMETHOD(pcib_release_msix, pci_dw_release_msix),
844 DEVMETHOD(pcib_map_msi, pci_dw_map_msi),
845 DEVMETHOD(pcib_get_id, pci_dw_get_id),
846
847 /* OFW bus interface */
848 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
849 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
850 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
851 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
852 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
853
854 /* PCI DW interface */
855 DEVMETHOD(pci_dw_dbi_read, pci_dw_dbi_read),
856 DEVMETHOD(pci_dw_dbi_write, pci_dw_dbi_write),
857 DEVMETHOD_END
858 };
859
860 DEFINE_CLASS_1(pcib, pci_dw_driver, pci_dw_methods,
861 sizeof(struct pci_dw_softc), ofw_pcib_driver);
862