Searched refs:MDIO_WC_REG_RX1_PCI_CTRL (Results 1 – 2 of 2) sorted by relevance
3371 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca macro
617 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca macro4673 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), in elink_warpcore_enable_AN_KR()